[PATCH] D105967: [TableGen] Allow isAllocatable inheritence from any superclass

[Carl Ritson via Phabricator via llvm-commits]

critson created this revision.
critson added reviewers: arsenm, foad, rampitec, qcolombet, craig.topper, kparzysz.
Herald added subscribers: atanasyan, arichardson, tpr, sdardis.
critson requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
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When setting Allocatable on a generated register class check all
superclasses and set Allocatable true if any superclass is
allocatable.

Without this change generated register classes based on an
allocatable class may end up unallocatable due to the topological
inheritance order.

This change primarily effects AMDGPU backend; however, there are
a few changes in MIPs GlobalISel register constraints as a result.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D105967

Files:
  llvm/utils/TableGen/CodeGenRegisters.cpp


Index: llvm/utils/TableGen/CodeGenRegisters.cpp
===================================================================
--- llvm/utils/TableGen/CodeGenRegisters.cpp
+++ llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -834,6 +834,12 @@
   VTs = Super.VTs;
   CopyCost = Super.CopyCost;
   Allocatable = Super.Allocatable;
+  if (!Allocatable) {
+    // Check for allocatable superclasses.
+    for (auto S = SuperClasses.rbegin();
+         S != SuperClasses.rend() && !Allocatable; ++S)
+      Allocatable |= (*S)->Allocatable;
+  }
   AltOrderSelect = Super.AltOrderSelect;
   AllocationPriority = Super.AllocationPriority;
   GeneratePressureSet |= Super.GeneratePressureSet;


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