[PATCH] D105214: [ARM] RELA relocations for 32bit ARM ignore the addend.
Wolfgang Pieb via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 13 11:06:06 PDT 2021
wolfgangp added a comment.
Ping. Any comments on this more RISCV-specific approach?
================
Comment at: llvm/test/DebugInfo/ARM/dwarfdump-rela.yaml:34
+ EntSize: 0x0
+ - Name: .rel.debug_info
+ Type: SHT_RELA
----------------
MaskRay wrote:
> rela
It it's OK with you, I fancy leaving the name as 'rel', just to make sure we don't key off the name of the section instead of the section type.
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https://reviews.llvm.org/D105214/new/
https://reviews.llvm.org/D105214
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