[PATCH] D105875: [RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions.
Jessica Clarke via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 13 06:19:31 PDT 2021
jrtc27 added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1006
+def PseudoBRIND : Pseudo<(outs), (ins GPRJALR:$rs1, simm12:$imm12), []>,
PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>;
----------------
This is one part of TableGen that I've never quite understood the rules about, but: does the expansion also need to use GPRJALR? (ditto for PseudoCALLIndirect)
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105875/new/
https://reviews.llvm.org/D105875
More information about the llvm-commits
mailing list