[PATCH] D105879: Refine logic of MaskedElementsAreZero

[Xiang Zhang via Phabricator via llvm-commits]

xiangzhangllvm created this revision.
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The Mask (DemandedBits ) passed to MaskedValueIsZero in MaskedElementsAreZero seems didn't make sense.
Try to refine it at first.


https://reviews.llvm.org/D105879

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2445,9 +2445,31 @@
 /// use this predicate to simplify operations downstream.
 bool SelectionDAG::MaskedElementsAreZero(SDValue Op, const APInt &DemandedElts,
                                          unsigned Depth) const {
+  APInt DemandedBits;
+  EVT VT = Op.getValueType();
   unsigned BitWidth = Op.getScalarValueSizeInBits();
-  APInt DemandedBits = APInt::getAllOnesValue(BitWidth);
-  return MaskedValueIsZero(Op, DemandedBits, DemandedElts, Depth);
+
+  if (VT.isVector()) {
+    unsigned NumElts = VT.getVectorNumElements();
+    assert(NumElts == DemandedElts.getBitWidth() && "Unexpected vector size");
+    DemandedBits = APInt::getNullValue(BitWidth * NumElts);
+    for (int i = 0; i < NumElts; i++) {
+      if (!DemandedElts[i])
+        continue;
+      DemandedBits.setBits(BitWidth * i, BitWidth * (i + 1));
+    }
+  } else {
+    DemandedBits = APInt::getAllOnesValue(BitWidth);
+  }
+
+  APInt Zero = computeKnownBits(Op, DemandedElts, Depth).Zero;
+
+  if (DemandedBits.getBitWidth() > Zero.getBitWidth())
+    Zero = Zero.zext(DemandedBits.getBitWidth());
+  else
+    Zero = Zero.trunc(DemandedBits.getBitWidth());
+
+  return DemandedBits.isSubsetOf(Zero);
 }
 
 /// MaskedValueIsAllOnes - Return true if '(Op & Mask) == Mask'.


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