[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via llvm-commits]

Jim added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:69
 
+def sub_lo : SubRegIndex<32>;
+def sub_hi : SubRegIndex<32, 32>;
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luismarques wrote:
> jrtc27 wrote:
> > This assumes RV32, and is not clear it applies to register pairs
> What's the best way to address this?
sub_lo and sub_hi are only used for GPRPair register class to extract a register from pair registers on RV32.


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  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588