[PATCH] D105742: [AMDGPU] Make V_CVT_I32_F64/V_CVT_F64_I32 rematerializable.

Stanislav Mekhanoshin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jul 9 16:09:38 PDT 2021


rampitec marked an inline comment as done.
rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:125
   default:
+    if (isVOP1(MI) || isVOP3(MI))
+      return !MI.hasImplicitDef() &&
----------------
arsenm wrote:
> arsenm wrote:
> > Braces
> What about VOP2?
There are no supported VOP2 yet. Only two VOP1 conversions and their promoted VOP3 forms.


================
Comment at: llvm/test/CodeGen/AMDGPU/remat-vop.mir:340
     S_ENDPGM 0
 ...
----------------
arsenm wrote:
> Can you add a test with a mode def that blocks rematerialization?
It is exist in `remat-vop.mir`, test `test_no_remat_v_cvt_i32_f64_e32_mode_def`.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105742/new/

https://reviews.llvm.org/D105742



More information about the llvm-commits mailing list