[PATCH] D105760: [AMDGPU] Handle s_branch to another section.

[Hafiz Abid Qadeer via Phabricator via llvm-commits]

abidh created this revision.
abidh added reviewers: dp, arsenm, tstellar.
Herald added subscribers: foad, kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl.
abidh requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

Currently, if target of s_branch instruction is in another section, it will fail with the error of undefined label.  Although in this case, the label is not undefined but present in another section. This patch tries to handle this issue. So while handling fixup_si_sopp_br fixup in getRelocType, if the target label is undefined we issue an error as before. If it is defined, a new relocation type R_AMDGPU_REL16 is returned.

This issue has been reported in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100181 and https://bugs.llvm.org/show_bug.cgi?id=45887. Before https://reviews.llvm.org/D79943, we used to get an crash for this scenario. The crash is fixed now but the we still get an undefined label error.  Jumps to other section can arise with hold/cold splitting.

A patch to handle the relocation in lld will follow shortly.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D105760

Files:
  llvm/docs/AMDGPUUsage.rst
  llvm/include/llvm/BinaryFormat/ELFRelocs/AMDGPU.def
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
  llvm/test/MC/AMDGPU/reloc.s
  llvm/test/Object/AMDGPU/elf64-relocs.yaml


Index: llvm/test/Object/AMDGPU/elf64-relocs.yaml
===================================================================
--- llvm/test/Object/AMDGPU/elf64-relocs.yaml
+++ llvm/test/Object/AMDGPU/elf64-relocs.yaml
@@ -16,6 +16,7 @@
 # CHECK:     0x20 R_AMDGPU_REL32_LO       - 0x0
 # CHECK:     0x22 R_AMDGPU_REL32_HI       - 0x0
 # CHECK:     0x24 R_AMDGPU_RELATIVE64     - 0x0
+# CHECK:     0x26 R_AMDGPU_REL16          - 0x0
 # CHECK:   }
 # CHECK: ]
 
@@ -62,6 +63,8 @@
         Type:            R_AMDGPU_REL32_HI
       - Offset:          0x24
         Type:            R_AMDGPU_RELATIVE64
+      - Offset:          0x26
+        Type:            R_AMDGPU_REL16
 
 Symbols:
   - Name:            .text
Index: llvm/test/MC/AMDGPU/reloc.s
===================================================================
--- llvm/test/MC/AMDGPU/reloc.s
+++ llvm/test/MC/AMDGPU/reloc.s
@@ -9,6 +9,7 @@
 // CHECK: R_AMDGPU_GOTPCREL32_HI global_var2
 // CHECK: R_AMDGPU_REL32_LO global_var3
 // CHECK: R_AMDGPU_REL32_HI global_var4
+// CHECK: R_AMDGPU_REL16 .text.unlikely
 // CHECK: R_AMDGPU_ABS32 var
 // CHECK: }
 // CHECK: .rel.data {
@@ -25,6 +26,11 @@
   s_mov_b32 s4, global_var2 at gotpcrel32@hi
   s_mov_b32 s5, global_var3 at rel32@lo
   s_mov_b32 s6, global_var4 at rel32@hi
+  s_branch cold
+
+  .section .text.unlikely
+cold:
+  s_add_i32 s15, s15, 1
 
 .globl global_var0
 .globl global_var1
Index: llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
+++ llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
@@ -80,9 +80,12 @@
     const auto *SymA = Target.getSymA();
     assert(SymA);
 
-    Ctx.reportError(Fixup.getLoc(),
-                    Twine("undefined label '") + SymA->getSymbol().getName() + "'");
-    return ELF::R_AMDGPU_NONE;
+    if (SymA->getSymbol().isUndefined()) {
+      Ctx.reportError(Fixup.getLoc(), Twine("undefined label '") +
+                                          SymA->getSymbol().getName() + "'");
+      return ELF::R_AMDGPU_NONE;
+    } else
+      return ELF::R_AMDGPU_REL16;
   }
 
   llvm_unreachable("unhandled relocation type");
Index: llvm/include/llvm/BinaryFormat/ELFRelocs/AMDGPU.def
===================================================================
--- llvm/include/llvm/BinaryFormat/ELFRelocs/AMDGPU.def
+++ llvm/include/llvm/BinaryFormat/ELFRelocs/AMDGPU.def
@@ -15,3 +15,4 @@
 ELF_RELOC(R_AMDGPU_REL32_LO,      10)
 ELF_RELOC(R_AMDGPU_REL32_HI,      11)
 ELF_RELOC(R_AMDGPU_RELATIVE64,    13)
+ELF_RELOC(R_AMDGPU_REL16,         14)
Index: llvm/docs/AMDGPUUsage.rst
===================================================================
--- llvm/docs/AMDGPUUsage.rst
+++ llvm/docs/AMDGPUUsage.rst
@@ -1574,6 +1574,7 @@
      ``R_AMDGPU_REL32_HI``      Static  11     ``word32``  (S + A - P) >> 32
      *reserved*                         12
      ``R_AMDGPU_RELATIVE64``    Dynamic 13     ``word64``  B + A
+     ``R_AMDGPU_REL16``         Static  14     ``word16``  ((S + A - P) - 4) / 4
      ========================== ======= =====  ==========  ==============================
 
 ``R_AMDGPU_ABS32_LO`` and ``R_AMDGPU_ABS32_HI`` are only supported by


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D105760.357727.patch
Type: text/x-patch
Size: 3243 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210710/45be9a74/attachment.bin>