[llvm] e2bc88f - [ARM] Extra v8i16 -> i64 reduction tests with loads. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 8 14:27:44 PDT 2021
Author: David Green
Date: 2021-07-08T22:27:23+01:00
New Revision: e2bc88f175400e06dffd217a86841d069870fb30
URL: https://github.com/llvm/llvm-project/commit/e2bc88f175400e06dffd217a86841d069870fb30
DIFF: https://github.com/llvm/llvm-project/commit/e2bc88f175400e06dffd217a86841d069870fb30.diff
LOG: [ARM] Extra v8i16 -> i64 reduction tests with loads. NFC
Added:
Modified:
llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll b/llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
index 395df61c1fa1e..3bf046edfaa07 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll
@@ -744,6 +744,216 @@ entry:
ret i64 %z
}
+define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_zext_load(<16 x i8> *%xp, <16 x i8> *%yp) {
+; CHECK-LABEL: add_v16i8_v16i64_zext_load:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .vsave {d8, d9}
+; CHECK-NEXT: vpush {d8, d9}
+; CHECK-NEXT: vldrw.u32 q1, [r1]
+; CHECK-NEXT: vmov.i64 q0, #0xff
+; CHECK-NEXT: vmov.u8 r1, q1[1]
+; CHECK-NEXT: vmov.u8 r2, q1[0]
+; CHECK-NEXT: vmov q2[2], q2[0], r2, r1
+; CHECK-NEXT: vand q3, q2, q0
+; CHECK-NEXT: vldrw.u32 q2, [r0]
+; CHECK-NEXT: vmov r1, s12
+; CHECK-NEXT: vmov.u8 r0, q2[1]
+; CHECK-NEXT: vmov.u8 r2, q2[0]
+; CHECK-NEXT: vmov q4[2], q4[0], r2, r0
+; CHECK-NEXT: vmov r2, s14
+; CHECK-NEXT: vand q4, q4, q0
+; CHECK-NEXT: vmov r0, s16
+; CHECK-NEXT: vmov r3, s18
+; CHECK-NEXT: umull r0, r12, r0, r1
+; CHECK-NEXT: vmov.u8 r1, q2[2]
+; CHECK-NEXT: smlabb r0, r3, r2, r0
+; CHECK-NEXT: vmov.u8 r2, q1[3]
+; CHECK-NEXT: vmov.u8 r3, q1[2]
+; CHECK-NEXT: vmov q3[2], q3[0], r3, r2
+; CHECK-NEXT: vmov.u8 r3, q2[3]
+; CHECK-NEXT: vmov q4[2], q4[0], r1, r3
+; CHECK-NEXT: vand q3, q3, q0
+; CHECK-NEXT: vand q4, q4, q0
+; CHECK-NEXT: vmov r2, s12
+; CHECK-NEXT: vmov r1, s16
+; CHECK-NEXT: vmov r3, s18
+; CHECK-NEXT: umull r1, r2, r1, r2
+; CHECK-NEXT: adds r0, r0, r1
+; CHECK-NEXT: adc.w r1, r12, r2
+; CHECK-NEXT: vmov r2, s14
+; CHECK-NEXT: umlal r0, r1, r3, r2
+; CHECK-NEXT: vmov.u8 r2, q1[5]
+; CHECK-NEXT: vmov.u8 r3, q1[4]
+; CHECK-NEXT: vmov q3[2], q3[0], r3, r2
+; CHECK-NEXT: vmov.u8 r3, q2[5]
+; CHECK-NEXT: vmov.u8 r2, q2[4]
+; CHECK-NEXT: vand q3, q3, q0
+; CHECK-NEXT: vmov q4[2], q4[0], r2, r3
+; CHECK-NEXT: vmov r12, s12
+; CHECK-NEXT: vand q4, q4, q0
+; CHECK-NEXT: vmov r2, s16
+; CHECK-NEXT: vmov r3, s18
+; CHECK-NEXT: umlal r0, r1, r2, r12
+; CHECK-NEXT: vmov r2, s14
+; CHECK-NEXT: umull r2, r3, r3, r2
+; CHECK-NEXT: adds r0, r0, r2
+; CHECK-NEXT: vmov.u8 r2, q1[7]
+; CHECK-NEXT: adcs r1, r3
+; CHECK-NEXT: vmov.u8 r3, q1[6]
+; CHECK-NEXT: vmov q3[2], q3[0], r3, r2
+; CHECK-NEXT: vmov.u8 r3, q2[7]
+; CHECK-NEXT: vmov.u8 r2, q2[6]
+; CHECK-NEXT: vand q3, q3, q0
+; CHECK-NEXT: vmov q4[2], q4[0], r2, r3
+; CHECK-NEXT: vmov r12, s12
+; CHECK-NEXT: vand q4, q4, q0
+; CHECK-NEXT: vmov r2, s16
+; CHECK-NEXT: vmov r3, s18
+; CHECK-NEXT: umlal r0, r1, r2, r12
+; CHECK-NEXT: vmov r2, s14
+; CHECK-NEXT: umull r2, r3, r3, r2
+; CHECK-NEXT: adds r0, r0, r2
+; CHECK-NEXT: vmov.u8 r2, q1[9]
+; CHECK-NEXT: adcs r1, r3
+; CHECK-NEXT: vmov.u8 r3, q1[8]
+; CHECK-NEXT: vmov q3[2], q3[0], r3, r2
+; CHECK-NEXT: vmov.u8 r3, q2[9]
+; CHECK-NEXT: vmov.u8 r2, q2[8]
+; CHECK-NEXT: vand q3, q3, q0
+; CHECK-NEXT: vmov q4[2], q4[0], r2, r3
+; CHECK-NEXT: vmov r12, s12
+; CHECK-NEXT: vand q4, q4, q0
+; CHECK-NEXT: vmov r2, s16
+; CHECK-NEXT: vmov r3, s18
+; CHECK-NEXT: umlal r0, r1, r2, r12
+; CHECK-NEXT: vmov r2, s14
+; CHECK-NEXT: umull r2, r3, r3, r2
+; CHECK-NEXT: adds r0, r0, r2
+; CHECK-NEXT: vmov.u8 r2, q1[11]
+; CHECK-NEXT: adcs r1, r3
+; CHECK-NEXT: vmov.u8 r3, q1[10]
+; CHECK-NEXT: vmov q3[2], q3[0], r3, r2
+; CHECK-NEXT: vmov.u8 r3, q2[11]
+; CHECK-NEXT: vmov.u8 r2, q2[10]
+; CHECK-NEXT: vand q3, q3, q0
+; CHECK-NEXT: vmov q4[2], q4[0], r2, r3
+; CHECK-NEXT: vmov r12, s12
+; CHECK-NEXT: vand q4, q4, q0
+; CHECK-NEXT: vmov r2, s16
+; CHECK-NEXT: vmov r3, s18
+; CHECK-NEXT: umlal r0, r1, r2, r12
+; CHECK-NEXT: vmov r2, s14
+; CHECK-NEXT: umull r2, r3, r3, r2
+; CHECK-NEXT: adds r0, r0, r2
+; CHECK-NEXT: vmov.u8 r2, q1[13]
+; CHECK-NEXT: adcs r1, r3
+; CHECK-NEXT: vmov.u8 r3, q1[12]
+; CHECK-NEXT: vmov q3[2], q3[0], r3, r2
+; CHECK-NEXT: vmov.u8 r3, q2[13]
+; CHECK-NEXT: vmov.u8 r2, q2[12]
+; CHECK-NEXT: vand q3, q3, q0
+; CHECK-NEXT: vmov q4[2], q4[0], r2, r3
+; CHECK-NEXT: vmov r12, s12
+; CHECK-NEXT: vand q4, q4, q0
+; CHECK-NEXT: vmov r2, s16
+; CHECK-NEXT: vmov r3, s18
+; CHECK-NEXT: umlal r0, r1, r2, r12
+; CHECK-NEXT: vmov r2, s14
+; CHECK-NEXT: umull r2, r3, r3, r2
+; CHECK-NEXT: adds r0, r0, r2
+; CHECK-NEXT: vmov.u8 r2, q1[15]
+; CHECK-NEXT: adcs r1, r3
+; CHECK-NEXT: vmov.u8 r3, q1[14]
+; CHECK-NEXT: vmov q1[2], q1[0], r3, r2
+; CHECK-NEXT: vmov.u8 r3, q2[15]
+; CHECK-NEXT: vmov.u8 r2, q2[14]
+; CHECK-NEXT: vand q1, q1, q0
+; CHECK-NEXT: vmov q2[2], q2[0], r2, r3
+; CHECK-NEXT: vmov r12, s4
+; CHECK-NEXT: vand q0, q2, q0
+; CHECK-NEXT: vmov r2, s0
+; CHECK-NEXT: vmov r3, s2
+; CHECK-NEXT: umlal r0, r1, r2, r12
+; CHECK-NEXT: vmov r2, s6
+; CHECK-NEXT: umull r2, r3, r3, r2
+; CHECK-NEXT: adds r0, r0, r2
+; CHECK-NEXT: adcs r1, r3
+; CHECK-NEXT: vpop {d8, d9}
+; CHECK-NEXT: bx lr
+entry:
+ %x = load <16 x i8>, <16 x i8>* %xp
+ %y = load <16 x i8>, <16 x i8>* %yp
+ %xx = zext <16 x i8> %x to <16 x i64>
+ %yy = zext <16 x i8> %y to <16 x i64>
+ %m = mul <16 x i64> %xx, %yy
+ %z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %m)
+ ret i64 %z
+}
+
+define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_sext_load(<16 x i8> *%xp, <16 x i8> *%yp) {
+; CHECK-LABEL: add_v16i8_v16i64_sext_load:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vldrw.u32 q0, [r1]
+; CHECK-NEXT: vldrw.u32 q1, [r0]
+; CHECK-NEXT: vmov.s8 r1, q0[1]
+; CHECK-NEXT: vmov.s8 r0, q1[1]
+; CHECK-NEXT: smull r0, r1, r0, r1
+; CHECK-NEXT: vmov.s8 r2, q0[0]
+; CHECK-NEXT: vmov.s8 r3, q1[0]
+; CHECK-NEXT: smlal r0, r1, r3, r2
+; CHECK-NEXT: vmov.s8 r2, q0[2]
+; CHECK-NEXT: vmov.s8 r3, q1[2]
+; CHECK-NEXT: smlal r0, r1, r3, r2
+; CHECK-NEXT: vmov.s8 r2, q0[3]
+; CHECK-NEXT: vmov.s8 r3, q1[3]
+; CHECK-NEXT: smlal r0, r1, r3, r2
+; CHECK-NEXT: vmov.s8 r2, q0[4]
+; CHECK-NEXT: vmov.s8 r3, q1[4]
+; CHECK-NEXT: smlal r0, r1, r3, r2
+; CHECK-NEXT: vmov.s8 r2, q0[5]
+; CHECK-NEXT: vmov.s8 r3, q1[5]
+; CHECK-NEXT: smlal r0, r1, r3, r2
+; CHECK-NEXT: vmov.s8 r2, q0[6]
+; CHECK-NEXT: vmov.s8 r3, q1[6]
+; CHECK-NEXT: smlal r0, r1, r3, r2
+; CHECK-NEXT: vmov.s8 r2, q0[7]
+; CHECK-NEXT: vmov.s8 r3, q1[7]
+; CHECK-NEXT: smlal r0, r1, r3, r2
+; CHECK-NEXT: vmov.s8 r2, q0[8]
+; CHECK-NEXT: vmov.s8 r3, q1[8]
+; CHECK-NEXT: smlal r0, r1, r3, r2
+; CHECK-NEXT: vmov.s8 r2, q0[9]
+; CHECK-NEXT: vmov.s8 r3, q1[9]
+; CHECK-NEXT: smlal r0, r1, r3, r2
+; CHECK-NEXT: vmov.s8 r2, q0[10]
+; CHECK-NEXT: vmov.s8 r3, q1[10]
+; CHECK-NEXT: smlal r0, r1, r3, r2
+; CHECK-NEXT: vmov.s8 r2, q0[11]
+; CHECK-NEXT: vmov.s8 r3, q1[11]
+; CHECK-NEXT: smlal r0, r1, r3, r2
+; CHECK-NEXT: vmov.s8 r2, q0[12]
+; CHECK-NEXT: vmov.s8 r3, q1[12]
+; CHECK-NEXT: smlal r0, r1, r3, r2
+; CHECK-NEXT: vmov.s8 r2, q0[13]
+; CHECK-NEXT: vmov.s8 r3, q1[13]
+; CHECK-NEXT: smlal r0, r1, r3, r2
+; CHECK-NEXT: vmov.s8 r2, q0[14]
+; CHECK-NEXT: vmov.s8 r3, q1[14]
+; CHECK-NEXT: smlal r0, r1, r3, r2
+; CHECK-NEXT: vmov.s8 r2, q0[15]
+; CHECK-NEXT: vmov.s8 r3, q1[15]
+; CHECK-NEXT: smlal r0, r1, r3, r2
+; CHECK-NEXT: bx lr
+entry:
+ %x = load <16 x i8>, <16 x i8>* %xp
+ %y = load <16 x i8>, <16 x i8>* %yp
+ %xx = sext <16 x i8> %x to <16 x i64>
+ %yy = sext <16 x i8> %y to <16 x i64>
+ %m = mul <16 x i64> %xx, %yy
+ %z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %m)
+ ret i64 %z
+}
+
define arm_aapcs_vfpcc i64 @add_v8i8_v8i64_zext(<8 x i8> %x, <8 x i8> %y) {
; CHECK-LABEL: add_v8i8_v8i64_zext:
; CHECK: @ %bb.0: @ %entry
@@ -1554,6 +1764,226 @@ entry:
ret i64 %r
}
+define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_acc_zext_load(<16 x i8> *%xp, <16 x i8> *%yp, i64 %a) {
+; CHECK-LABEL: add_v16i8_v16i64_acc_zext_load:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r4, lr}
+; CHECK-NEXT: push {r4, lr}
+; CHECK-NEXT: .vsave {d8, d9}
+; CHECK-NEXT: vpush {d8, d9}
+; CHECK-NEXT: vldrw.u32 q1, [r1]
+; CHECK-NEXT: vmov.i64 q0, #0xff
+; CHECK-NEXT: vmov.u8 r12, q1[1]
+; CHECK-NEXT: vmov.u8 r1, q1[0]
+; CHECK-NEXT: vmov q2[2], q2[0], r1, r12
+; CHECK-NEXT: vand q3, q2, q0
+; CHECK-NEXT: vldrw.u32 q2, [r0]
+; CHECK-NEXT: vmov r12, s12
+; CHECK-NEXT: vmov.u8 r0, q2[1]
+; CHECK-NEXT: vmov.u8 r1, q2[0]
+; CHECK-NEXT: vmov q4[2], q4[0], r1, r0
+; CHECK-NEXT: vmov r1, s14
+; CHECK-NEXT: vand q4, q4, q0
+; CHECK-NEXT: vmov.u8 r4, q2[2]
+; CHECK-NEXT: vmov r0, s16
+; CHECK-NEXT: umull lr, r12, r0, r12
+; CHECK-NEXT: vmov r0, s18
+; CHECK-NEXT: smlabb lr, r0, r1, lr
+; CHECK-NEXT: vmov.u8 r1, q1[3]
+; CHECK-NEXT: vmov.u8 r0, q1[2]
+; CHECK-NEXT: vmov q3[2], q3[0], r0, r1
+; CHECK-NEXT: vmov.u8 r1, q2[3]
+; CHECK-NEXT: vmov q4[2], q4[0], r4, r1
+; CHECK-NEXT: vand q3, q3, q0
+; CHECK-NEXT: vand q4, q4, q0
+; CHECK-NEXT: vmov r0, s12
+; CHECK-NEXT: vmov r1, s16
+; CHECK-NEXT: vmov r4, s18
+; CHECK-NEXT: umull r0, r1, r1, r0
+; CHECK-NEXT: adds.w r0, r0, lr
+; CHECK-NEXT: vmov.u8 lr, q2[5]
+; CHECK-NEXT: adc.w r1, r1, r12
+; CHECK-NEXT: vmov r12, s14
+; CHECK-NEXT: umlal r0, r1, r4, r12
+; CHECK-NEXT: vmov.u8 r12, q1[5]
+; CHECK-NEXT: vmov.u8 r4, q1[4]
+; CHECK-NEXT: vmov q3[2], q3[0], r4, r12
+; CHECK-NEXT: vmov.u8 r4, q2[4]
+; CHECK-NEXT: vmov q4[2], q4[0], r4, lr
+; CHECK-NEXT: vand q3, q3, q0
+; CHECK-NEXT: vand q4, q4, q0
+; CHECK-NEXT: vmov r12, s12
+; CHECK-NEXT: vmov r4, s16
+; CHECK-NEXT: vmov.u8 lr, q2[7]
+; CHECK-NEXT: umlal r0, r1, r4, r12
+; CHECK-NEXT: vmov r12, s14
+; CHECK-NEXT: vmov r4, s18
+; CHECK-NEXT: umull r4, r12, r4, r12
+; CHECK-NEXT: adds r0, r0, r4
+; CHECK-NEXT: vmov.u8 r4, q1[6]
+; CHECK-NEXT: adc.w r1, r1, r12
+; CHECK-NEXT: vmov.u8 r12, q1[7]
+; CHECK-NEXT: vmov q3[2], q3[0], r4, r12
+; CHECK-NEXT: vmov.u8 r4, q2[6]
+; CHECK-NEXT: vmov q4[2], q4[0], r4, lr
+; CHECK-NEXT: vand q3, q3, q0
+; CHECK-NEXT: vand q4, q4, q0
+; CHECK-NEXT: vmov r12, s12
+; CHECK-NEXT: vmov r4, s16
+; CHECK-NEXT: vmov.u8 lr, q2[9]
+; CHECK-NEXT: umlal r0, r1, r4, r12
+; CHECK-NEXT: vmov r12, s14
+; CHECK-NEXT: vmov r4, s18
+; CHECK-NEXT: umull r4, r12, r4, r12
+; CHECK-NEXT: adds r0, r0, r4
+; CHECK-NEXT: vmov.u8 r4, q1[8]
+; CHECK-NEXT: adc.w r1, r1, r12
+; CHECK-NEXT: vmov.u8 r12, q1[9]
+; CHECK-NEXT: vmov q3[2], q3[0], r4, r12
+; CHECK-NEXT: vmov.u8 r4, q2[8]
+; CHECK-NEXT: vmov q4[2], q4[0], r4, lr
+; CHECK-NEXT: vand q3, q3, q0
+; CHECK-NEXT: vand q4, q4, q0
+; CHECK-NEXT: vmov r12, s12
+; CHECK-NEXT: vmov r4, s16
+; CHECK-NEXT: vmov.u8 lr, q2[11]
+; CHECK-NEXT: umlal r0, r1, r4, r12
+; CHECK-NEXT: vmov r12, s14
+; CHECK-NEXT: vmov r4, s18
+; CHECK-NEXT: umull r4, r12, r4, r12
+; CHECK-NEXT: adds r0, r0, r4
+; CHECK-NEXT: vmov.u8 r4, q1[10]
+; CHECK-NEXT: adc.w r1, r1, r12
+; CHECK-NEXT: vmov.u8 r12, q1[11]
+; CHECK-NEXT: vmov q3[2], q3[0], r4, r12
+; CHECK-NEXT: vmov.u8 r4, q2[10]
+; CHECK-NEXT: vmov q4[2], q4[0], r4, lr
+; CHECK-NEXT: vand q3, q3, q0
+; CHECK-NEXT: vand q4, q4, q0
+; CHECK-NEXT: vmov r12, s12
+; CHECK-NEXT: vmov r4, s16
+; CHECK-NEXT: vmov.u8 lr, q2[13]
+; CHECK-NEXT: umlal r0, r1, r4, r12
+; CHECK-NEXT: vmov r12, s14
+; CHECK-NEXT: vmov r4, s18
+; CHECK-NEXT: umull r4, r12, r4, r12
+; CHECK-NEXT: adds r0, r0, r4
+; CHECK-NEXT: vmov.u8 r4, q1[12]
+; CHECK-NEXT: adc.w r1, r1, r12
+; CHECK-NEXT: vmov.u8 r12, q1[13]
+; CHECK-NEXT: vmov q3[2], q3[0], r4, r12
+; CHECK-NEXT: vmov.u8 r4, q2[12]
+; CHECK-NEXT: vmov q4[2], q4[0], r4, lr
+; CHECK-NEXT: vand q3, q3, q0
+; CHECK-NEXT: vand q4, q4, q0
+; CHECK-NEXT: vmov r12, s12
+; CHECK-NEXT: vmov r4, s16
+; CHECK-NEXT: vmov.u8 lr, q2[15]
+; CHECK-NEXT: umlal r0, r1, r4, r12
+; CHECK-NEXT: vmov r12, s14
+; CHECK-NEXT: vmov r4, s18
+; CHECK-NEXT: umull r4, r12, r4, r12
+; CHECK-NEXT: adds r0, r0, r4
+; CHECK-NEXT: vmov.u8 r4, q1[14]
+; CHECK-NEXT: adc.w r1, r1, r12
+; CHECK-NEXT: vmov.u8 r12, q1[15]
+; CHECK-NEXT: vmov q1[2], q1[0], r4, r12
+; CHECK-NEXT: vmov.u8 r4, q2[14]
+; CHECK-NEXT: vmov q2[2], q2[0], r4, lr
+; CHECK-NEXT: vand q1, q1, q0
+; CHECK-NEXT: vand q0, q2, q0
+; CHECK-NEXT: vmov r12, s4
+; CHECK-NEXT: vmov r4, s0
+; CHECK-NEXT: umlal r0, r1, r4, r12
+; CHECK-NEXT: vmov r12, s6
+; CHECK-NEXT: vmov r4, s2
+; CHECK-NEXT: umull r4, r12, r4, r12
+; CHECK-NEXT: adds r0, r0, r4
+; CHECK-NEXT: adc.w r1, r1, r12
+; CHECK-NEXT: adds r0, r0, r2
+; CHECK-NEXT: adcs r1, r3
+; CHECK-NEXT: vpop {d8, d9}
+; CHECK-NEXT: pop {r4, pc}
+entry:
+ %x = load <16 x i8>, <16 x i8>* %xp
+ %y = load <16 x i8>, <16 x i8>* %yp
+ %xx = zext <16 x i8> %x to <16 x i64>
+ %yy = zext <16 x i8> %y to <16 x i64>
+ %m = mul <16 x i64> %xx, %yy
+ %z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %m)
+ %r = add i64 %z, %a
+ ret i64 %r
+}
+
+define arm_aapcs_vfpcc i64 @add_v16i8_v16i64_acc_sext_load(<16 x i8> *%xp, <16 x i8> *%yp, i64 %a) {
+; CHECK-LABEL: add_v16i8_v16i64_acc_sext_load:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: .save {r7, lr}
+; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: vldrw.u32 q0, [r1]
+; CHECK-NEXT: vldrw.u32 q1, [r0]
+; CHECK-NEXT: vmov.s8 r1, q0[1]
+; CHECK-NEXT: vmov.s8 r0, q1[1]
+; CHECK-NEXT: smull r0, lr, r0, r1
+; CHECK-NEXT: vmov.s8 r12, q0[0]
+; CHECK-NEXT: vmov.s8 r1, q1[0]
+; CHECK-NEXT: smlal r0, lr, r1, r12
+; CHECK-NEXT: vmov.s8 r12, q0[2]
+; CHECK-NEXT: vmov.s8 r1, q1[2]
+; CHECK-NEXT: smlal r0, lr, r1, r12
+; CHECK-NEXT: vmov.s8 r12, q0[3]
+; CHECK-NEXT: vmov.s8 r1, q1[3]
+; CHECK-NEXT: smlal r0, lr, r1, r12
+; CHECK-NEXT: vmov.s8 r12, q0[4]
+; CHECK-NEXT: vmov.s8 r1, q1[4]
+; CHECK-NEXT: smlal r0, lr, r1, r12
+; CHECK-NEXT: vmov.s8 r12, q0[5]
+; CHECK-NEXT: vmov.s8 r1, q1[5]
+; CHECK-NEXT: smlal r0, lr, r1, r12
+; CHECK-NEXT: vmov.s8 r12, q0[6]
+; CHECK-NEXT: vmov.s8 r1, q1[6]
+; CHECK-NEXT: smlal r0, lr, r1, r12
+; CHECK-NEXT: vmov.s8 r12, q0[7]
+; CHECK-NEXT: vmov.s8 r1, q1[7]
+; CHECK-NEXT: smlal r0, lr, r1, r12
+; CHECK-NEXT: vmov.s8 r12, q0[8]
+; CHECK-NEXT: vmov.s8 r1, q1[8]
+; CHECK-NEXT: smlal r0, lr, r1, r12
+; CHECK-NEXT: vmov.s8 r12, q0[9]
+; CHECK-NEXT: vmov.s8 r1, q1[9]
+; CHECK-NEXT: smlal r0, lr, r1, r12
+; CHECK-NEXT: vmov.s8 r12, q0[10]
+; CHECK-NEXT: vmov.s8 r1, q1[10]
+; CHECK-NEXT: smlal r0, lr, r1, r12
+; CHECK-NEXT: vmov.s8 r12, q0[11]
+; CHECK-NEXT: vmov.s8 r1, q1[11]
+; CHECK-NEXT: smlal r0, lr, r1, r12
+; CHECK-NEXT: vmov.s8 r12, q0[12]
+; CHECK-NEXT: vmov.s8 r1, q1[12]
+; CHECK-NEXT: smlal r0, lr, r1, r12
+; CHECK-NEXT: vmov.s8 r12, q0[13]
+; CHECK-NEXT: vmov.s8 r1, q1[13]
+; CHECK-NEXT: smlal r0, lr, r1, r12
+; CHECK-NEXT: vmov.s8 r12, q0[14]
+; CHECK-NEXT: vmov.s8 r1, q1[14]
+; CHECK-NEXT: smlal r0, lr, r1, r12
+; CHECK-NEXT: vmov.s8 r12, q0[15]
+; CHECK-NEXT: vmov.s8 r1, q1[15]
+; CHECK-NEXT: smlal r0, lr, r1, r12
+; CHECK-NEXT: adds r0, r0, r2
+; CHECK-NEXT: adc.w r1, lr, r3
+; CHECK-NEXT: pop {r7, pc}
+entry:
+ %x = load <16 x i8>, <16 x i8>* %xp
+ %y = load <16 x i8>, <16 x i8>* %yp
+ %xx = sext <16 x i8> %x to <16 x i64>
+ %yy = sext <16 x i8> %y to <16 x i64>
+ %m = mul <16 x i64> %xx, %yy
+ %z = call i64 @llvm.vector.reduce.add.v16i64(<16 x i64> %m)
+ %r = add i64 %z, %a
+ ret i64 %r
+}
+
define arm_aapcs_vfpcc i64 @add_v2i8_v2i64_acc_zext(<2 x i8> %x, <2 x i8> %y, i64 %a) {
; CHECK-LABEL: add_v2i8_v2i64_acc_zext:
; CHECK: @ %bb.0: @ %entry
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