[PATCH] D94097: [AArch64] Legalize MVT::i64x8 in DAG isel lowering.

[Tim Northover via Phabricator via llvm-commits]

t.p.northover added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:8252
+  if (Subtarget->hasLS64())
+    if (ArrayType *ATy = dyn_cast<ArrayType>(Ty))
+      if (ATy->getNumElements() == 8 && ATy->getElementType()->isIntegerTy(64))
----------------
This looks like it turns all `[8 x i64]` IR types into `i64x8`, which is pretty risky.

At the very least it means we probably need to add new tests for any natural IR operation you can do to that type (load, store, extract, insert, alloca, GEP, phi, select, function calls & returns and anything else you can think of to throw at it).


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94097/new/

https://reviews.llvm.org/D94097