[PATCH] D105617: [PowerPC] Fix addi-load bias scheduling heuristics

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf created this revision.
qiucf added reviewers: shchenz, jsji, nemanjai, PowerPC.
Herald added subscribers: javed.absar, kbarton, hiraditya, MatzeB.
qiucf requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

1. `LI`/`LI8` are also some form of `ADDI`
2. Fixed the function to check it, the second one should be `mayLoad`, not `!isADDI`

According to generated inc file, `mtctr` is also seen as `mayLoad`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D105617

Files:
  llvm/lib/Target/PowerPC/PPCMachineScheduler.cpp
  llvm/test/CodeGen/PowerPC/aix-p9-xxinsertw-xxextractuw.ll
  llvm/test/CodeGen/PowerPC/aix-vec_extract_p9.ll
  llvm/test/CodeGen/PowerPC/aix-vec_extract_p9_2.ll
  llvm/test/CodeGen/PowerPC/aix-vec_insert_elt.ll
  llvm/test/CodeGen/PowerPC/global-address-non-got-indirect-access.ll
  llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
  llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll
  llvm/test/CodeGen/PowerPC/pr48519.ll
  llvm/test/CodeGen/PowerPC/sms-simple.ll
  llvm/test/CodeGen/PowerPC/unaligned-addressing-mode.ll
  llvm/test/CodeGen/PowerPC/vec_insert_elt.ll

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