[PATCH] D105589: [ARM] Move the creation of VBICIMM and VORRIMM to lowering

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

In D105589#2863135 <https://reviews.llvm.org/D105589#2863135>, @efriedma wrote:

> If you just want to delay the combine, I'd suggest just adding a `DCI.isAfterLegalizeDAG()` to the existing DAGCombine.  Doing it during lowering can lead to weird results; for example, AArch64 currently does this, and there's testcase where we end up with `orr v0.2s, #0`.

The buildvectors will not be legal at that point, and the VBIC will be a different set of immediates to VMOVIMM. That was how I first attempted it.  But I think I would prefer not to rewrite the transform if it will just be replaced in the future.


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