[PATCH] D104471: [llvm][sve] Lowering for VLS truncating stores

[Bradley Smith via Phabricator via llvm-commits]

bsmith added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll:150-151
 ; VBITS_GE_2048-NEXT: uzp1 [[UZP2:z[0-9]+]].h, [[UZP1]].h, [[UZP1]].h
-; VBITS_GE_2048-NEXT: uzp1 [[UZP3:z[0-9]+]].b, [[UZP2]].b, [[UZP2]].b
-; VBITS_GE_2048-NEXT: st1b { [[UZP3]].b }, [[PG0]], [x0]
+; VBITS_GE_2048-NEXT: uzp1 z[[UZP3:[0-9]+]].b, [[UZP2]].b, [[UZP2]].b
+; VBITS_GE_2048-NEXT: st1b { [[RES]].b }, [[PG0]], [x0]
 ; VBITS_GE_2048-NEXT: ret
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This test change looks incorrect


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  https://reviews.llvm.org/D104471/new/

https://reviews.llvm.org/D104471