[PATCH] D105417: [RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/add-before-shl.ll:42
 ; RV64I-NEXT:    slli a0, a0, 48
+; RV64I-NEXT:    lui a1, 4095
+; RV64I-NEXT:    slli a1, a1, 36
----------------
As noted in D79492 this is a regression for the C extension as lui a1, 4095 isn't compressible, but the lui 1 and addiw -1 were.

The cost model used by isDesirableToCommuteWithShift doesn't understand compressed instructions.


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Comment at: llvm/test/CodeGen/RISCV/rv64zbp.ll:3621
 ; RV64I-NEXT:    slli a2, a0, 4
+; RV64I-NEXT:    lui a3, 983055
+; RV64I-NEXT:    slli a3, a3, 4
----------------
This is a regression. We lose out on coincidental CSE of part of the materialization of two similar constants 0x00F000F000F000F0 and 0x0F000F000F000F00. They have the same number of 1s but are shifted 4 bits relative to each other.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D105417/new/

https://reviews.llvm.org/D105417