[PATCH] D104394: [MachineCopyPropagation] Fix differences in code gen when compiling with -g
Kai Luo via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 2 04:27:29 PDT 2021
This revision was automatically updated to reflect the committed changes.
Closed by commit rGe90c6f559637: [MachineCopyPropagation] Fix differences in code gen when compiling with -g (authored by Alexandru Octavian Butiu <alexandru.octavian.butiu at gmail.com>, committed by lkail).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D104394/new/
https://reviews.llvm.org/D104394
Files:
llvm/lib/CodeGen/MachineCopyPropagation.cpp
llvm/test/CodeGen/X86/machine-copy-dbgvalue.mir
Index: llvm/test/CodeGen/X86/machine-copy-dbgvalue.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/machine-copy-dbgvalue.mir
@@ -0,0 +1,20 @@
+# RUN: llc -mtriple=i686-- -run-pass machine-cp -verify-machineinstrs -o - %s | FileCheck %s
+
+
+---
+# Test that machine copy propagation ignores DBG_VALUE and DBL_VALUE_LIST and updates it.
+# CHECK-LABEL: name: foo
+# CHECK: bb.0:
+# CHECK-NEXT: $rax = MOV64ri 31
+# CHECK-NEXT: DBG_VALUE $rax
+# CHECK-NEXT: DBG_VALUE_LIST 0, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_constu, 4, DW_OP_mul, DW_OP_plus, DW_OP_stack_value), $rax, 0, 0
+# CHECK-NEXT: RETQ implicit killed $rax
+name: foo
+body: |
+ bb.0:
+ renamable $rcx = MOV64ri 31
+ DBG_VALUE $rcx, 0, 0, 0, 0
+ DBG_VALUE_LIST 0, !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_constu, 4, DW_OP_mul, DW_OP_plus, DW_OP_stack_value), $rcx, 0, 0
+ $rax = COPY killed renamable $rcx
+ RETQ implicit killed $rax
+...
Index: llvm/lib/CodeGen/MachineCopyPropagation.cpp
===================================================================
--- llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -870,12 +870,32 @@
if (MO.isDef())
Tracker.invalidateRegister(MO.getReg().asMCReg(), *TRI);
- if (MO.readsReg())
- Tracker.invalidateRegister(MO.getReg().asMCReg(), *TRI);
+ if (MO.readsReg()) {
+ if (MO.isDebug()) {
+ // Check if the register in the debug instruction is utilized
+ // in a copy instruction, so we can update the debug info if the
+ // register is changed.
+ for (MCRegUnitIterator RUI(MO.getReg().asMCReg(), TRI); RUI.isValid();
+ ++RUI) {
+ if (auto *Copy = Tracker.findCopyDefViaUnit(*RUI, *TRI)) {
+ CopyDbgUsers[Copy].insert(MI);
+ }
+ }
+ } else {
+ Tracker.invalidateRegister(MO.getReg().asMCReg(), *TRI);
+ }
+ }
}
}
for (auto *Copy : MaybeDeadCopies) {
+
+ Register Src = Copy->getOperand(1).getReg();
+ Register Def = Copy->getOperand(0).getReg();
+ SmallVector<MachineInstr *> MaybeDeadDbgUsers(CopyDbgUsers[Copy].begin(),
+ CopyDbgUsers[Copy].end());
+
+ MRI->updateDbgUsersToReg(Src.asMCReg(), Def.asMCReg(), MaybeDeadDbgUsers);
Copy->eraseFromParent();
++NumDeletes;
}
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