[PATCH] D104471: [llvm][sve] Lowering for VLS truncating stores

[David Truby via Phabricator via llvm-commits]

DavidTruby updated this revision to Diff 355926.
DavidTruby added a comment.
Herald added subscribers: foad, kerbowa, atanasyan, jrtc27, nhaehnle, jvesely, sdardis, arsenm.

Here I've fixed the test breakages on MIPS and AMDGPU

I believe the new MIPS code generated is both correct and better 
than the existing code generation but I'd like someone more 
familiar with the architecture than me to verify that!

The AMDGPU change is more involved, as it revolves around the fact
that truncating stores of vectors are not supported on R600 from
what I understand. As such we don't want to tell the DAG combiner
that we want more truncating stores. I'm not really sure what
I've done here is the "correct" way to handle this, it feels a bit
hacky to me to be honest, so if anyone has any better suggestions 
I would like to hear them


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104471/new/

https://reviews.llvm.org/D104471

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AMDGPU/R600ISelLowering.h
  llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll
  llvm/test/CodeGen/Mips/cconv/byval.ll
  llvm/test/CodeGen/Mips/cconv/vector.ll
  llvm/test/CodeGen/Mips/llvm-ir/store.ll
  llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll

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