[PATCH] D104000: GlobalISel: Use LLT in memory legality queries

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jun 30 11:44:20 PDT 2021


arsenm added a comment.

In D104000#2850901 <https://reviews.llvm.org/D104000#2850901>, @aemerson wrote:

> Why did the AArch64 tests change?

Because this wasn't properly handling non-byte accesses. The current DAG behavior is to zero the high bits on store, and insert AssertZext on load. When the legalizer handles this, it makes the special case s1 handling in the selector dead (the selector won't even see an s1 memory type)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104000/new/

https://reviews.llvm.org/D104000



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