[llvm] fcd0cb3 - Fix MSVC "32-bit shift implicitly converted to 64 bits" warning.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 30 05:25:05 PDT 2021
Author: Simon Pilgrim
Date: 2021-06-30T13:23:53+01:00
New Revision: fcd0cb39214e5abc89bfb1926397fe668172ecaa
URL: https://github.com/llvm/llvm-project/commit/fcd0cb39214e5abc89bfb1926397fe668172ecaa
DIFF: https://github.com/llvm/llvm-project/commit/fcd0cb39214e5abc89bfb1926397fe668172ecaa.diff
LOG: Fix MSVC "32-bit shift implicitly converted to 64 bits" warning.
Added:
Modified:
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 7126977a00f6d..280140f009209 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1920,7 +1920,7 @@ HexagonTargetLowering::validateConstPtrAlignment(SDValue Ptr, Align NeedAlign,
return;
unsigned Addr = CA->getZExtValue();
Align HaveAlign =
- Addr != 0 ? Align(1u << countTrailingZeros(Addr)) : NeedAlign;
+ Addr != 0 ? Align(1ull << countTrailingZeros(Addr)) : NeedAlign;
if (HaveAlign < NeedAlign) {
std::string ErrMsg;
raw_string_ostream O(ErrMsg);
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