[PATCH] D105033: [TableGen] Allow identical MnemonicAliases with no predicate

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

In D105033#2844486 <https://reviews.llvm.org/D105033#2844486>, @nlguillemot wrote:

> In the code sample in the description, is it supposed to be `Feature_Subtarget2Bit` for the second "if"?

Yes, sorry about that. Fixed.

> One thing I'm wondering is, how about defining the MnemonicAlias just once outside the multiclass?

Well, yes. The problem with simplifying the example enough to fit in a commit message, is that it makes it look simple to fix by rewriting the td file. The real world example is more complicated. And yes I'm sure I //could// fix it by changing the td file, but I was hoping you all would take my word for it that it's pretty awkward to do that.

To show you the complete real world example I would have to spend some time making it open-source-able. But the multiclass I'm really interested in is analogous to:

  multiclass VOP1Inst <string opName, VOPProfile P,
                       SDPatternOperator node = null_frag> {
    // We only want to set this on the basic, non-SDWA or DPP forms.
    defvar should_mov_imm = !eq(opName, "v_mov_b32");
  
    let isMoveImm = should_mov_imm in {
      def _e32 : VOP1_Pseudo <opName, P>;
      def _e64 : VOP3_Pseudo <opName, P, getVOP1Pat64<node, P>.ret>;
    }
  
    foreach _ = BoolToList<P.HasExtSDWA>.ret in
      def _sdwa : VOP1_SDWA_Pseudo <opName, P>;
  
    foreach _ = BoolToList<P.HasExtDPP>.ret in
      def _dpp : VOP1_DPP_Pseudo <opName, P>;
  
    def : MnemonicAlias<opName#"_e32", opName>, LetDummies;
    def : MnemonicAlias<opName#"_e64", opName>, LetDummies;
  
    foreach _ = BoolToList<P.HasExtSDWA>.ret in
      def : MnemonicAlias<opName#"_sdwa", opName>, LetDummies;
  
    foreach _ = BoolToList<P.HasExtDPP>.ret in
      def : MnemonicAlias<opName#"_dpp", opName>, LetDummies;
  }

And it's used something like this:

  let SubtargetPredicate = isGFX7GFX8GFX9 in {
    let TRANS = 1, SchedRW = [WriteTrans32] in {
      defm V_LOG_LEGACY_F32 : VOP1Inst<"v_log_legacy_f32", VOP_F32_F32>;
      defm V_EXP_LEGACY_F32 : VOP1Inst<"v_exp_legacy_f32", VOP_F32_F32>;
    } // End TRANS = 1, SchedRW = [WriteTrans32]
  } // End SubtargetPredicate = isGFX7GFX8GFX9

And note that the way the predicate is set on the instructions with `let SubtargetPredicate =` (where SubtargetPredicate is used by a class called PredicateControl which is a superclass of VOP1_Pseudo, VOP3_Pseudo et al) does //not// automatically set a corresponding predicate on the MnemonicAliases defined by the multiclass.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105033/new/

https://reviews.llvm.org/D105033