[PATCH] D105016: [TargetLowering][AArch64][SVE] Take into account accessed type when clamping address

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:7796
     if (auto *IdxCst = dyn_cast<ConstantSDNode>(Idx))
-      if (IdxCst->getZExtValue() < NElts)
+      if (IdxCst->getZExtValue() + NumSubElts <= NElts)
         return Idx;
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bsmith wrote:
> peterwaller-arm wrote:
> > Question: Shouldn't this remain `<`? My thinking: Logically, the thing on the left is the maximum index, and when you increment that thing, it needs to remain less than NElts to still be a valid index.
> Not quite, if `NumSubElts` is 1, then the index is `IdxCst->getZExtValue()`, not `IdxCst->getZExtValue() + 1`. Perhaps it's better to think of this like the following:
> 
> `IdxCst->getZExtValue() + (NumSubElts - 1) < NElts`
This looks better, thanks for clarifying.

Perhaps the comment on the if statement could be updated to account for the fact an n-element subvec is involved.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105016/new/

https://reviews.llvm.org/D105016