[PATCH] D104903: [X86] Limit the scaled element type to i64/f64

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

This has scaringly many magic numbers.



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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:43639
+  int Size = VT.getVectorNumElements();
   if (VT.is256BitVector() && Subtarget.hasInt256()) {
     SmallVector<int> Mask0, Mask1;
----------------
Since the final shuffle has element type of i64/f64,
should this enforce that the source element type is less than that?


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:43664-43666
+          for (int I = 0; I < 4; ++I)
+            if (ShuffleMask[I] != ScaledMask1[I])
+              return SDValue();
----------------
So what this checking is that `ScaledMask0 == ScaledMask1` (i.e. scaled Mask0 and Mask1 are identical)?
Again, special-casing `8` seems weird.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104903/new/

https://reviews.llvm.org/D104903