[PATCH] D104836: [PowerPC] Combine 64-bit bswap(load) without LDBRX

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added a comment.

In D104836#2838555 <https://reviews.llvm.org/D104836#2838555>, @spatel wrote:

> LangRef says "the backend should never split or merge target-legal volatile load/store instructions":
> https://llvm.org/docs/LangRef.html#volatile-memory-accesses
>
> I haven't looked at the use cases in detail, but the target does support 64-bit loads via plain `ld`, so we shouldn't do the transform?

Hmm... clearly this requirement cannot possibly be met for `volatile` operations that are wider than the available load for the target. Of course, that is not the case here. So I suppose it is possible for a volatile load to load the two halves of the value before and after a store to the same memory from another thread.
I'll add the volatile check and bail on the combine. Thanks for bringing this up.


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