[PATCH] D104836: [PowerPC] Combine 64-bit bswap(load) without LDBRX

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

LangRef says "the backend should never split or merge target-legal volatile load/store instructions":
https://llvm.org/docs/LangRef.html#volatile-memory-accesses

I haven't looked at the use cases in detail, but the target does support 64-bit loads via plain `ld`, so we shouldn't do the transform?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D104836/new/

https://reviews.llvm.org/D104836