[PATCH] D104727: [RISCV] Permit RVV stack offsets larger than 12 bits

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 accepted this revision.
rogfer01 added a comment.
This revision is now accepted and ready to land.

> Strictly speaking it's not 12-bit stack offsets we're now supporting but rather a 12-bit "number of vector registers". For whatever reason I was unable to find a concise way of explaining this in the commit message/description so if anyone's got a better way I'm all ears.

I think "number of vector registers" may be good enough. This seems difficult to describe because the offsets in the scalable vector stackid have their offsets conceptually scaled to the smallest `vscale` possible (=1), so the code counts how many registers (currently 8 bytes per VR under `vscale=1`) are contained in (the unscaled) `Amount` to later scale that using `vlenb`.

I'm curious when you hit this. Asking because, unless I'm reading the testcase wrong, you're computing a `NumOfVReg` that seems huge (3072?)

Other than that LGTM. Thanks @frasercrmck


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104727/new/

https://reviews.llvm.org/D104727