[PATCH] D104264: Fix atomic loads and stores of 64-bit values in non-default address spaces on ARM

[David Chisnall via Phabricator via llvm-commits]

theraven added a comment.

To elaborate: The set of possible invalid IR is huge and back ends are permitted to assume that they are only ever provided with valid IR, as per the informal contract between the back end and the rest of the compiler (including requiring function arguments to be arranged in a way that the back end's ABI-lowering logic understands).  Ensuring that the back end is only ever given IR that it knows how to consume is the responsibility of whatever is invoking the back end.  In an ideal world, every construct that a front end + optimiser pipeline may feed to a back end would have a test in tests/Target/{back end} that would check that it correctly lowers the IR.

I don't have any objection to the ARM back ends generating an error if they encounter a pointer in an unknown address space, but I also don't object if that error is an assertion failure or an `llvm::unreachable`, and it's also fine for it to crash because there are a load of other cases of IR that you can feed into a back end to make it crash if you try hard enough.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104264/new/

https://reviews.llvm.org/D104264