[PATCH] D104440: [X86] Fix bug when X86 stackify pass handle one ArgFPRW.

[LuoYuanke via Phabricator via llvm-commits]

LuoYuanke added a comment.

> Does this fix your test
>
>   diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp
>   index 44670a9..3e5d45b 100644
>   --- a/llvm/lib/Target/X86/X86FastISel.cpp
>   +++ b/llvm/lib/Target/X86/X86FastISel.cpp
>   @@ -3842,6 +3842,30 @@ unsigned X86FastISel::fastMaterializeConstant(const Constant *C) {
>        return X86MaterializeFP(CFP, VT);
>      else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
>        return X86MaterializeGV(GV, VT);
>   +  else if (isa<UndefValue>(C)) {
>   +    unsigned Opc = 0;
>   +    switch (VT.SimpleTy) {
>   +    default:
>   +      break;
>   +    case MVT::f32:
>   +      if (!X86ScalarSSEf32)
>   +        Opc = X86::LD_Fp032;
>   +      break;
>   +    case MVT::f64:
>   +      if (!X86ScalarSSEf64)
>   +        Opc = X86::LD_Fp064;
>   +      break;
>   +    case MVT::f80:
>   +      Opc = X86::LD_Fp080;
>   +      break;
>   +    }
>   +
>   +    if (Opc) {
>   +      Register ResultReg = createResultReg(TLI.getRegClassFor(VT));
>   +      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
>   +      return ResultReg;
>   +    }
>   +  }
>    
>      return 0;
>    }

Yes. It can fix. Thank you! One question, is there any other consideration to prevent undef float value in MIR? Otherwise stackify pass can support undef value by insert fld0 instruction, so that all ISel passes don't have to handle it specially.


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https://reviews.llvm.org/D104440