[PATCH] D104371: [compiler-rt] Avoid unnecessary AArch64 DSB in __clear_cache in some situations.

[Kristof Beyls via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG6f0e74cd583b: Avoid unnecessary AArch64 DSB in __clear_cache in some situations. (authored by kristof.beyls).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104371/new/

https://reviews.llvm.org/D104371

Files:
  compiler-rt/lib/builtins/clear_cache.c


Index: compiler-rt/lib/builtins/clear_cache.c
===================================================================
--- compiler-rt/lib/builtins/clear_cache.c
+++ compiler-rt/lib/builtins/clear_cache.c
@@ -127,8 +127,8 @@
     for (addr = xstart & ~(icache_line_size - 1); addr < xend;
          addr += icache_line_size)
       __asm __volatile("ic ivau, %0" ::"r"(addr));
+    __asm __volatile("dsb ish");
   }
-  __asm __volatile("dsb ish");
   __asm __volatile("isb sy");
 #elif defined(__powerpc64__)
   const size_t line_size = 32;


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