[llvm] 7f3ac67 - [AMDGPU] Set SALU, VALU and other instruction type flags on Real instructions
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 16 05:37:17 PDT 2021
Author: Jay Foad
Date: 2021-06-16T13:36:02+01:00
New Revision: 7f3ac6714a561553500cbd24331a8dc7f2375964
URL: https://github.com/llvm/llvm-project/commit/7f3ac6714a561553500cbd24331a8dc7f2375964
DIFF: https://github.com/llvm/llvm-project/commit/7f3ac6714a561553500cbd24331a8dc7f2375964.diff
LOG: [AMDGPU] Set SALU, VALU and other instruction type flags on Real instructions
This does not affect codegen but might benefit llvm-mca.
Added:
Modified:
llvm/lib/Target/AMDGPU/SOPInstructions.td
llvm/lib/Target/AMDGPU/VOP1Instructions.td
llvm/lib/Target/AMDGPU/VOP2Instructions.td
llvm/lib/Target/AMDGPU/VOPCInstructions.td
llvm/lib/Target/AMDGPU/VOPInstructions.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 3c2b4751f78a..437890b32a6b 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -59,6 +59,8 @@ class SOP1_Real<bits<8> op, SOP1_Pseudo ps, string real_name = ps.Mnemonic> :
real_name # " " # ps.AsmOperands, []>,
Enc32 {
+ let SALU = 1;
+ let SOP1 = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
let Size = 4;
@@ -370,6 +372,8 @@ class SOP2_Real<bits<7> op, SOP_Pseudo ps, string real_name = ps.Mnemonic> :
InstSI <ps.OutOperandList, ps.InOperandList,
real_name # " " # ps.AsmOperands, []>,
Enc32 {
+ let SALU = 1;
+ let SOP2 = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
@@ -703,6 +707,8 @@ class SOPK_Pseudo <string opName, dag outs, dag ins,
class SOPK_Real<bits<5> op, SOPK_Pseudo ps> :
InstSI <ps.OutOperandList, ps.InOperandList,
ps.Mnemonic # " " # ps.AsmOperands, []> {
+ let SALU = 1;
+ let SOPK = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
@@ -960,6 +966,8 @@ class SOPC_Real<bits<7> op, SOPC_Pseudo ps, string real_name = ps.Mnemonic> :
InstSI <ps.OutOperandList, ps.InOperandList,
real_name # " " # ps.AsmOperands, []>,
Enc32 {
+ let SALU = 1;
+ let SOPC = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
@@ -1091,6 +1099,8 @@ class SOPPRelaxTable <bit isRelaxed, string keyName, string gfxip> {
class SOPP_Real<bits<7> op, SOPP_Pseudo ps, string real_name = ps.Mnemonic> :
InstSI <ps.OutOperandList, ps.InOperandList,
real_name # ps.AsmOperands, []> {
+ let SALU = 1;
+ let SOPP = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index c4879a6a978d..69ae2af7708b 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -64,6 +64,8 @@ class VOP1_Real <VOP1_Pseudo ps, int EncodingFamily> :
InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
SIMCInstr <ps.PseudoInstr, EncodingFamily> {
+ let VALU = 1;
+ let VOP1 = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
@@ -83,6 +85,7 @@ class VOP1_Real <VOP1_Pseudo ps, int EncodingFamily> :
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
+ let TRANS = ps.TRANS;
}
class VOP1_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
@@ -500,6 +503,7 @@ class VOP1_DPP<bits<8> op, VOP1_DPP_Pseudo ps, VOPProfile p = ps.Pfl, bit isDPP1
let Defs = ps.Defs;
let SchedRW = ps.SchedRW;
let Uses = ps.Uses;
+ let TRANS = ps.TRANS;
bits<8> vdst;
let Inst{8-0} = 0xfa;
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 0a1bb9a81a80..6ad23bc7497a 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -85,6 +85,8 @@ class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> :
InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
SIMCInstr <ps.PseudoInstr, EncodingFamily> {
+ let VALU = 1;
+ let VOP2 = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
index 169054fd30f0..c0cc91029d11 100644
--- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -104,6 +104,8 @@ class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily> :
InstSI <ps.OutOperandList, ps.InOperandList, ps.PseudoInstr # " " # ps.AsmOperands, []>,
SIMCInstr <ps.PseudoInstr, EncodingFamily> {
+ let VALU = 1;
+ let VOPC = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index 813941af0847..5f6f664ea3e7 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -150,6 +150,8 @@ class VOP3_Real <VOP_Pseudo ps, int EncodingFamily> :
InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
SIMCInstr <ps.PseudoInstr, EncodingFamily> {
+ let VALU = 1;
+ let VOP3 = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
let UseNamedOperandTable = 1;
@@ -171,6 +173,7 @@ class VOP3_Real <VOP_Pseudo ps, int EncodingFamily> :
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
+ let TRANS = ps.TRANS;
VOPProfile Pfl = ps.Pfl;
}
@@ -523,6 +526,8 @@ class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> :
InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA> {
+ let VALU = 1;
+ let SDWA = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
@@ -546,11 +551,14 @@ class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> :
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
+ let TRANS = ps.TRANS;
}
class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands9, []> {
+ let VALU = 1;
+ let SDWA = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
@@ -576,6 +584,7 @@ class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
+ let TRANS = ps.TRANS;
}
class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
@@ -655,6 +664,8 @@ class VOP_DPP_Real <VOP_DPP_Pseudo ps, int EncodingFamily> :
InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
SIMCInstr <ps.PseudoInstr, EncodingFamily> {
+ let VALU = 1;
+ let DPP = 1;
let isPseudo = 0;
let isCodeGenOnly = 0;
@@ -679,6 +690,7 @@ class VOP_DPP_Real <VOP_DPP_Pseudo ps, int EncodingFamily> :
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
+ let TRANS = ps.TRANS;
}
class VOP_DPP <string OpName, VOPProfile P, bit IsDPP16,
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