[llvm] 39efbf9 - [X86][AVX] Regenerate pr15296.ll tests

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-06-16T13:42:25+01:00
New Revision: 39efbf91361ea7e8ee988f6fca386cb1f97f0736

URL: https://github.com/llvm/llvm-project/commit/39efbf91361ea7e8ee988f6fca386cb1f97f0736
DIFF: https://github.com/llvm/llvm-project/commit/39efbf91361ea7e8ee988f6fca386cb1f97f0736.diff

LOG: [X86][AVX] Regenerate pr15296.ll tests

Exposes some really bad shift lowering codegen in shiftInput___canonical

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/pr15296.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/pr15296.ll b/llvm/test/CodeGen/X86/pr15296.ll
index 1187d80cdf75..71034f696429 100644
--- a/llvm/test/CodeGen/X86/pr15296.ll
+++ b/llvm/test/CodeGen/X86/pr15296.ll
@@ -1,6 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-pc-linux -mcpu=corei7-avx | FileCheck %s
 
 define <8 x i32> @shiftInput___vyuunu(<8 x i32> %input, i32 %shiftval, <8 x i32> %__mask) nounwind {
+; CHECK-LABEL: shiftInput___vyuunu:
+; CHECK:       # %bb.0: # %allocas
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; CHECK-NEXT:    vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; CHECK-NEXT:    vpsrld %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:    vpsrld %xmm2, %xmm0, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
 allocas:
   %smear.0 = insertelement <8 x i32> undef, i32 %shiftval, i32 0
   %smear.1 = insertelement <8 x i32> %smear.0, i32 %shiftval, i32 1
@@ -14,12 +23,32 @@ allocas:
   ret <8 x i32> %bitop
 }
 
-; CHECK: shiftInput___vyuunu
-; CHECK: psrld
-; CHECK: psrld
-; CHECK: ret
-
 define <8 x i32> @shiftInput___canonical(<8 x i32> %input, i32 %shiftval, <8 x i32> %__mask) nounwind {
+; CHECK-LABEL: shiftInput___canonical:
+; CHECK:       # %bb.0: # %allocas
+; CHECK-NEXT:    vbroadcastss {{[0-9]+}}(%esp), %xmm1
+; CHECK-NEXT:    vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm3
+; CHECK-NEXT:    vpsrld %xmm2, %xmm3, %xmm4
+; CHECK-NEXT:    vpsrlq $32, %xmm1, %xmm5
+; CHECK-NEXT:    vpsrld %xmm5, %xmm3, %xmm6
+; CHECK-NEXT:    vpblendw {{.*#+}} xmm4 = xmm6[0,1,2,3],xmm4[4,5,6,7]
+; CHECK-NEXT:    vpxor %xmm6, %xmm6, %xmm6
+; CHECK-NEXT:    vpblendw {{.*#+}} xmm6 = xmm1[0,1],xmm6[2,3,4,5,6,7]
+; CHECK-NEXT:    vpsrld %xmm6, %xmm3, %xmm7
+; CHECK-NEXT:    vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
+; CHECK-NEXT:    vpsrld %xmm1, %xmm3, %xmm3
+; CHECK-NEXT:    vpblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm7[4,5,6,7]
+; CHECK-NEXT:    vpblendw {{.*#+}} xmm3 = xmm3[0,1],xmm4[2,3],xmm3[4,5],xmm4[6,7]
+; CHECK-NEXT:    vpsrld %xmm2, %xmm0, %xmm2
+; CHECK-NEXT:    vpsrld %xmm5, %xmm0, %xmm4
+; CHECK-NEXT:    vpsrld %xmm6, %xmm0, %xmm5
+; CHECK-NEXT:    vpsrld %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vpblendw {{.*#+}} xmm1 = xmm4[0,1,2,3],xmm2[4,5,6,7]
+; CHECK-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm5[4,5,6,7]
+; CHECK-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
+; CHECK-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; CHECK-NEXT:    retl
 allocas:
   %smear.0 = insertelement <8 x i32> undef, i32 %shiftval, i32 0
   %smear.7 = shufflevector <8 x i32> %smear.0, <8 x i32> undef, <8 x i32> zeroinitializer
@@ -27,20 +56,18 @@ allocas:
   ret <8 x i32> %bitop
 }
 
-; CHECK: shiftInput___canonical
-; CHECK: psrld
-; CHECK: psrld
-; CHECK: ret
-
 define <4 x i64> @shiftInput___64in32bitmode(<4 x i64> %input, i64 %shiftval, <4 x i64> %__mask) nounwind {
+; CHECK-LABEL: shiftInput___64in32bitmode:
+; CHECK:       # %bb.0: # %allocas
+; CHECK-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; CHECK-NEXT:    vmovddup {{.*#+}} xmm2 = mem[0,0]
+; CHECK-NEXT:    vpsrlq %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:    vpsrlq %xmm2, %xmm0, %xmm0
+; CHECK-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    retl
 allocas:
   %smear.0 = insertelement <4 x i64> undef, i64 %shiftval, i32 0
   %smear.7 = shufflevector <4 x i64> %smear.0, <4 x i64> undef, <4 x i32> zeroinitializer
   %bitop = lshr <4 x i64> %input, %smear.7
   ret <4 x i64> %bitop
 }
-
-; CHECK: shiftInput___64in32bitmode
-; CHECK: psrlq
-; CHECK: psrlq
-; CHECK: ret