[PATCH] D104069: [RISCV] Teach vsetvli insertion to remember when predecessors have same AVL and SEW/LMUL ratio if their VTYPEs otherwise mismatch.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:227
 
-    if (*this == Other)
       return *this;
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I'm wondering if removing this use of the `==` operator is a sign we shouldn't have one for these types. Is it confusing to have different meaning of equality? Alternatively perhaps this operator is now unused so can be axed without much discussion.


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Comment at: llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll:501
+; We need a vsetvli in the last block because the predecessors have different
+; VTYPEs. The AVL is the same the SEW/LMUL ratio implies the same VLMAX so
+; we don't need to read AVL and can keep VL unchanged.
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Nit but this comment feels like it's missing something in `The AVL is the same the SEW/LMUL ratio`. A comma, or an `and`?


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https://reviews.llvm.org/D104069