[PATCH] D104264: Fix atomic loads and stores of 64-bit values in non-default address spaces on ARM

[Renato Golin via Phabricator via llvm-commits]

rengolin added a comment.

In D104264#2819829 <https://reviews.llvm.org/D104264#2819829>, @arsenm wrote:

> They are target defined. You're only doing this for this one target, so you can make them mean whatever you want them to mean

Right, I'm just not sure they mean what this patch wants them to mean for address space usage (indistinguishable for load/store purposes) on all uses and variations of Arm uarch/extensions.

I'm not finding many examples of address space cast codegen in Clang/LLVM other than GPU code.

I know CHERI uses address space for their capabilities and I don't think it would work to just cast it to non-capability world like that.


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https://reviews.llvm.org/D104264