[PATCH] D104156: [DAGCombine][X86][ARM] EXTRACT_SUBVECTOR(VECTOR_SHUFFLE(?,?,Mask)) -> VECTOR_SHUFFLE(EXTRACT_SUBVECTOR(?, ?), EXTRACT_SUBVECTOR(?, ?), Mask')

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

In D104156#2819328 <https://reviews.llvm.org/D104156#2819328>, @RKSimon wrote:

> In D104156#2818946 <https://reviews.llvm.org/D104156#2818946>, @lebedev.ri wrote:
>
>> So i'm not sure the rest can be dealt with by `SimplifyMultipleUseDemandedBits()`.
>
> What if the ZERO_EXTEND_VECTOR_INREG case is extended to just bitcast the source if we only need the 0th element and the upper source elements aliasing that 0th element is known to be zero?

But in that snippet they are clearly not zeros, since it's a splat vector?


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