[PATCH] D104156: [DAGCombine][X86][ARM] EXTRACT_SUBVECTOR(VECTOR_SHUFFLE(?,?,Mask)) -> VECTOR_SHUFFLE(EXTRACT_SUBVECTOR(?, ?), EXTRACT_SUBVECTOR(?, ?), Mask')

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In D104156#2818946 <https://reviews.llvm.org/D104156#2818946>, @lebedev.ri wrote:

> So i'm not sure the rest can be dealt with by `SimplifyMultipleUseDemandedBits()`.

What if the ZERO_EXTEND_VECTOR_INREG case is extended to just bitcast the source if we only need the 0th element and the upper source elements aliasing that 0th element is known to be zero?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D104156/new/

https://reviews.llvm.org/D104156