[PATCH] D104115: [SVE] Fix PromoteIntRes_TRUNCATE not to call getVectorNumElements
Dylan Fleming via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 11 06:06:10 PDT 2021
DylanFleming-arm created this revision.
Herald added subscribers: psnobl, hiraditya, tschuett.
Herald added a reviewer: efriedma.
DylanFleming-arm requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D104115
Files:
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/test/CodeGen/AArch64/sve-trunc.ll
Index: llvm/test/CodeGen/AArch64/sve-trunc.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-trunc.ll
+++ llvm/test/CodeGen/AArch64/sve-trunc.ll
@@ -183,3 +183,18 @@
%out = trunc <vscale x 16 x i8> %in to <vscale x 16 x i1>
ret <vscale x 16 x i1> %out
}
+
+define void @trunc_promoteIntRes(<vscale x 4 x i64> %0) {
+; CHECK-LABEL: trunc_promoteIntRes:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
+; CHECK-NEXT: ptrue p0.s
+; CHECK-NEXT: st1h { z0.s }, p0, [x8]
+; CHECK-NEXT: ret
+entry:
+ %1 = trunc <vscale x 4 x i64> %0 to <vscale x 4 x i16>
+ %2 = bitcast i16* undef to <vscale x 4 x i16>*
+ store <vscale x 4 x i16> %1, <vscale x 4 x i16>* %2, align 2
+ ret void
+}
+
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1239,17 +1239,17 @@
case TargetLowering::TypeSplitVector: {
EVT InVT = InOp.getValueType();
assert(InVT.isVector() && "Cannot split scalar types");
- unsigned NumElts = InVT.getVectorNumElements();
- assert(NumElts == NVT.getVectorNumElements() &&
+ ElementCount NumElts = InVT.getVectorElementCount();
+ assert(NumElts == NVT.getVectorElementCount() &&
"Dst and Src must have the same number of elements");
- assert(isPowerOf2_32(NumElts) &&
+ assert(isPowerOf2_32(NumElts.getKnownMinValue()) &&
"Promoted vector type must be a power of two");
SDValue EOp1, EOp2;
GetSplitVector(InOp, EOp1, EOp2);
EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
- NumElts/2);
+ NumElts.divideCoefficientBy(2));
EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
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