[PATCH] D104070: [AArch64][GlobalISel] Fix incorrectly generating uxtw/sxtw for addressing modes.

[Amara Emerson via Phabricator via llvm-commits]

aemerson created this revision.
aemerson added reviewers: paquette, jroelofs.
aemerson added a project: LLVM.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, rovka.
aemerson requested review of this revision.

When the extend is from 8 or 16 bits, the addressing modes don't support those extensions, but we weren't checking that and therefore always generated the 32->64b extension mode. Fun.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D104070

Files:
  llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir

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