[PATCH] D103170: [CodeGen][AArch64][SVE] Use ld1r[bhsd] for vector splat from memory

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Maybe add a testcase for splat of a constant?  Not sure what the code generation should look like, but it would be good to have coverage.



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Comment at: llvm/test/CodeGen/AArch64/sve-ld1r.ll:301
+; CHECK-NEXT:    ldr w8, [x0, #256]
+; CHECK-NEXT:    mov z0.s, w8
+; CHECK-NEXT:    ret
----------------
Is ldr+mov really better than add+ld1rw?  (I think it's coming out this way because SelectAddrModeIndexedUImm bails instead of forcing the offset to zero.)


Repository:
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https://reviews.llvm.org/D103170