[llvm] 292f419 - [RISCV] Fix failing RVV MC tests
Fraser Cormack via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 9 01:55:29 PDT 2021
Author: Fraser Cormack
Date: 2021-06-09T09:47:18+01:00
New Revision: 292f4197249bec40143c88fe3fea50d038676889
URL: https://github.com/llvm/llvm-project/commit/292f4197249bec40143c88fe3fea50d038676889
DIFF: https://github.com/llvm/llvm-project/commit/292f4197249bec40143c88fe3fea50d038676889.diff
LOG: [RISCV] Fix failing RVV MC tests
I believe these failures were introduced by D103790's changes to the
VType formatting found in vsetvli/vsetivli instructions.
Added:
Modified:
llvm/test/MC/RISCV/rvv/snippet.s
llvm/test/MC/RISCV/rvv/vsetvl.s
Removed:
################################################################################
diff --git a/llvm/test/MC/RISCV/rvv/snippet.s b/llvm/test/MC/RISCV/rvv/snippet.s
index a9115f94edf82..a5c19b0f18b5a 100644
--- a/llvm/test/MC/RISCV/rvv/snippet.s
+++ b/llvm/test/MC/RISCV/rvv/snippet.s
@@ -6,7 +6,7 @@
loop:
vsetvli a3, a0, e16,m4,ta,ma # vtype = 16-bit integer vectors
-# CHECK-INST: d7 76 a5 0c vsetvli a3, a0, e16,m4,ta,ma
+# CHECK-INST: d7 76 a5 0c vsetvli a3, a0, e16, m4, ta, ma
vle16.v v4, (a1) # Get 16b vector
# CHECK-INST: 07 d2 05 02 vle16.v v4, (a1)
slli t1, a3, 1 # Multiply length by two bytes/element
@@ -17,7 +17,7 @@ loop:
# CHECK-INST: 57 64 45 ee vwmul.vx v8, v4, a0
vsetvli x0, a0, e32,m8,ta,ma # Operate on 32b values
-# CHECK-INST: 57 70 35 0d vsetvli zero, a0, e32,m8,ta,ma
+# CHECK-INST: 57 70 35 0d vsetvli zero, a0, e32, m8, ta, ma
vsrl.vi v8, v8, 3
# CHECK-INST: 57 b4 81 a2 vsrl.vi v8, v8, 3
vse32.v v8, (a2) # Store vector of 32b
diff --git a/llvm/test/MC/RISCV/rvv/vsetvl.s b/llvm/test/MC/RISCV/rvv/vsetvl.s
index d792908627a66..85650d00447c8 100644
--- a/llvm/test/MC/RISCV/rvv/vsetvl.s
+++ b/llvm/test/MC/RISCV/rvv/vsetvl.s
@@ -8,68 +8,68 @@
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
-vsetvli a2, a0, e32,m1,ta,ma
-# CHECK-INST: vsetvli a2, a0, e32,m1,ta,ma
+vsetvli a2, a0, e32, m1, ta, ma
+# CHECK-INST: vsetvli a2, a0, e32, m1, ta, ma
# CHECK-ENCODING: [0x57,0x76,0x05,0x0d]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 76 05 0d <unknown>
-vsetvli a2, a0, e32,m2,ta,ma
-# CHECK-INST: vsetvli a2, a0, e32,m2,ta,ma
+vsetvli a2, a0, e32, m2, ta, ma
+# CHECK-INST: vsetvli a2, a0, e32, m2, ta, ma
# CHECK-ENCODING: [0x57,0x76,0x15,0x0d]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 76 15 0d <unknown>
-vsetvli a2, a0, e32,m4,ta,ma
-# CHECK-INST: vsetvli a2, a0, e32,m4,ta,ma
+vsetvli a2, a0, e32, m4, ta, ma
+# CHECK-INST: vsetvli a2, a0, e32, m4, ta, ma
# CHECK-ENCODING: [0x57,0x76,0x25,0x0d]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 76 25 0d <unknown>
-vsetvli a2, a0, e32,m8,ta,ma
-# CHECK-INST: vsetvli a2, a0, e32,m8,ta,ma
+vsetvli a2, a0, e32, m8, ta, ma
+# CHECK-INST: vsetvli a2, a0, e32, m8, ta, ma
# CHECK-ENCODING: [0x57,0x76,0x35,0x0d]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 76 35 0d <unknown>
-vsetvli a2, a0, e32,mf2,ta,ma
-# CHECK-INST: vsetvli a2, a0, e32,mf2,ta,ma
+vsetvli a2, a0, e32, mf2, ta, ma
+# CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma
# CHECK-ENCODING: [0x57,0x76,0x75,0x0d]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 76 75 0d <unknown>
-vsetvli a2, a0, e32,mf4,ta,ma
-# CHECK-INST: vsetvli a2, a0, e32,mf4,ta,ma
+vsetvli a2, a0, e32, mf4, ta, ma
+# CHECK-INST: vsetvli a2, a0, e32, mf4, ta, ma
# CHECK-ENCODING: [0x57,0x76,0x65,0x0d]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 76 65 0d <unknown>
-vsetvli a2, a0, e32,mf8,ta,ma
-# CHECK-INST: vsetvli a2, a0, e32,mf8,ta,ma
+vsetvli a2, a0, e32, mf8, ta, ma
+# CHECK-INST: vsetvli a2, a0, e32, mf8, ta, ma
# CHECK-ENCODING: [0x57,0x76,0x55,0x0d]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 76 55 0d <unknown>
-vsetvli a2, a0, e32,m1,ta,ma
-# CHECK-INST: vsetvli a2, a0, e32,m1,ta,ma
+vsetvli a2, a0, e32, m1, ta, ma
+# CHECK-INST: vsetvli a2, a0, e32, m1, ta, ma
# CHECK-ENCODING: [0x57,0x76,0x05,0x0d]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 76 05 0d <unknown>
-vsetvli a2, a0, e32,m1,tu,ma
-# CHECK-INST: vsetvli a2, a0, e32,m1,tu,ma
+vsetvli a2, a0, e32, m1, tu, ma
+# CHECK-INST: vsetvli a2, a0, e32, m1, tu, ma
# CHECK-ENCODING: [0x57,0x76,0x05,0x09]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 76 05 09 <unknown>
-vsetvli a2, a0, e32,m1,ta,mu
-# CHECK-INST: vsetvli a2, a0, e32,m1,ta,mu
+vsetvli a2, a0, e32, m1, ta, mu
+# CHECK-INST: vsetvli a2, a0, e32, m1, ta, mu
# CHECK-ENCODING: [0x57,0x76,0x05,0x05]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 76 05 05 <unknown>
-vsetvli a2, a0, e32,m1,tu,mu
-# CHECK-INST: vsetvli a2, a0, e32,m1
+vsetvli a2, a0, e32, m1, tu, mu
+# CHECK-INST: vsetvli a2, a0, e32, m1
# CHECK-ENCODING: [0x57,0x76,0x05,0x01]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 76 05 01 <unknown>
@@ -80,20 +80,20 @@ vsetvl a2, a0, a1
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 76 b5 80 <unknown>
-vsetivli a2, 0, e32,m1,ta,ma
-# CHECK-INST: vsetivli a2, 0, e32,m1,ta,ma
+vsetivli a2, 0, e32, m1, ta, ma
+# CHECK-INST: vsetivli a2, 0, e32, m1, ta, ma
# CHECK-ENCODING: [0x57,0x76,0x00,0xcd]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 76 00 cd <unknown>
-vsetivli a2, 15, e32,m1,ta,ma
-# CHECK-INST: vsetivli a2, 15, e32,m1,ta,ma
+vsetivli a2, 15, e32, m1, ta, ma
+# CHECK-INST: vsetivli a2, 15, e32, m1, ta, ma
# CHECK-ENCODING: [0x57,0xf6,0x07,0xcd]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 f6 07 cd <unknown>
-vsetivli a2, 31, e32,m1,ta,ma
-# CHECK-INST: vsetivli a2, 31, e32,m1,ta,ma
+vsetivli a2, 31, e32, m1, ta, ma
+# CHECK-INST: vsetivli a2, 31, e32, m1, ta, ma
# CHECK-ENCODING: [0x57,0xf6,0x0f,0xcd]
# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
# CHECK-UNKNOWN: 57 f6 0f cd <unknown>
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