[PATCH] D103939: [SVE][LSR] Teach LSR to enable simple scaled-index addressing mode generation for SVE.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11811
+           (AM.Scale == 0 || AM.Scale == 1 ||
+            (AM.Scale > 0 && (uint64_t)AM.Scale == VecElemNumBytes));
+  }
----------------
"AM.Scale > 0" check is redundant.


================
Comment at: llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:743
+          SmallVector<const SCEV *, 4> ROps(drop_begin(MulRHS->operands()));
+          if (SE.getMulExpr(LOps) == SE.getMulExpr(ROps))
+            return getExactSDiv(LC, RC, SE, IgnoreSignificantBits);
----------------
LOps == ROps?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103939/new/

https://reviews.llvm.org/D103939