[PATCH] D103939: [SVE][LSR] Teach LSR to enable simple scaled-index addressing mode generation for SVE.

[Huihui Zhang via Phabricator via llvm-commits]

huihuiz created this revision.
huihuiz added reviewers: efriedma, sdesmalen, paulwalker-arm, david-arm, bsmith, kmclaughlin, t.p.northover, greened, samparker.
huihuiz added a project: LLVM.
Herald added subscribers: psnobl, arphaman, hiraditya, kristof.beyls, tschuett.
huihuiz requested review of this revision.

Currently, Loop strengh reduce is not handling loops with scalable stride very well.

Take loop vectorized with scalable vector type <vscale x 8 x i16> for instance,
(refer to test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll added).

Memory accesses are incremented by "16*vscale", while induction variable is incremented
by "8*vscale". The scaling factor "2" needs to be extracted to build candidate formula
i.e., "reg(%in) + 2*reg({0,+,(8 * %vscale)}". So that addrec register reg({0,+,(8*vscale)})
can be reused among Address and ICmpZero LSRUses to enable optimal solution selection.

This patch allow LSR getExactSDiv to recognize special cases like "C1*X*Y /s C2*X*Y",
and pull out "C1 /s C2" as scaling factor whenever possible. Without this change, LSR
is missing candidate formula with proper scaled factor to leverage target scaled-index
addressing mode.

Note: This patch doesn't fully fix AArch64 isLegalAddressingMode for scalable
vector. But allow simple valid scale to pass through.
(<-- I am not very confident fixing AArch64 isLegalAddressingMode for SVE, your help/comments are highly appreciated).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103939

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
  llvm/test/CodeGen/AArch64/sve-fold-vscale.ll
  llvm/test/CodeGen/AArch64/sve-lsr-scaled-index-addressing-mode.ll

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