[PATCH] D103925: [X86][SSE] Support 64-bit vectorization (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: ABataev, xbolva00, pengfei, spatel, craig.topper.
Herald added a subscriber: hiraditya.
RKSimon requested review of this revision.
Herald added a project: LLVM.

Based off bugs such as:

https://bugs.llvm.org/show_bug.cgi?id=47491
https://bugs.llvm.org/show_bug.cgi?id=49933

This is a WIP patch investigating x86 supporting vectorizing to 64-bit vector widths. Although 128-bits is the minimum architectural vector width on SSE targets, we do have fast load/stores for 64-bits and we've widened all shorter vector types to 128-bits for some time so there should be no extension/truncation nastiness to get in the way.

The description for getMinVectorRegisterBitWidth() is "The width of the smallest vector register type" - if there's concern that we're stretching this too far, we could add an new 'getMinVectorizationBitWidth()' TTI call that calls getMinVectorRegisterBitWidth() by default and use that. But at the moment only SLP and VectorCombiner actually uses it.

Before pursuing this further we need to be very confident that the cost tables are good enough for non-legal types, in particular for conversion ops (ext, trunc, int<->fp etc.) where the number of legalized vector elements don't match - my work on D103695 <https://reviews.llvm.org/D103695> should help here.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D103925

Files:
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/lib/Target/X86/X86TargetTransformInfo.h
  llvm/test/Transforms/SLPVectorizer/X86/addsub.ll
  llvm/test/Transforms/SLPVectorizer/X86/alternate-calls-inseltpoison.ll
  llvm/test/Transforms/SLPVectorizer/X86/alternate-calls.ll
  llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
  llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
  llvm/test/Transforms/SLPVectorizer/X86/commutativity.ll
  llvm/test/Transforms/SLPVectorizer/X86/crash_7zip.ll
  llvm/test/Transforms/SLPVectorizer/X86/crash_bullet.ll
  llvm/test/Transforms/SLPVectorizer/X86/crash_bullet3.ll
  llvm/test/Transforms/SLPVectorizer/X86/crash_sim4b1.ll
  llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
  llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
  llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
  llvm/test/Transforms/SLPVectorizer/X86/insertvalue.ll
  llvm/test/Transforms/SLPVectorizer/X86/no_alternate_divrem.ll
  llvm/test/Transforms/SLPVectorizer/X86/phi.ll
  llvm/test/Transforms/SLPVectorizer/X86/pr42022-inseltpoison.ll
  llvm/test/Transforms/SLPVectorizer/X86/pr42022.ll
  llvm/test/Transforms/SLPVectorizer/X86/remark_not_all_parts.ll
  llvm/test/Transforms/SLPVectorizer/X86/reorder_phi.ll
  llvm/test/Transforms/SLPVectorizer/X86/rgb_phi.ll
  llvm/test/Transforms/SLPVectorizer/X86/saxpy.ll
  llvm/test/Transforms/SLPVectorizer/X86/schedule-bundle.ll
  llvm/test/Transforms/SLPVectorizer/X86/schedule_budget.ll
  llvm/test/Transforms/SLPVectorizer/X86/simple-loop.ll
  llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
  llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
  llvm/test/Transforms/SLPVectorizer/X86/tiny-tree.ll
  llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
  llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
  llvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
  llvm/test/Transforms/VectorCombine/X86/load.ll

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