[PATCH] D101469: [RISCV] Enable interleaved vectorization for RVV

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/test/Transforms/LoopVectorize/RISCV/riscv-interleaved.ll:11-50
+define dso_local void @foo(i32 signext %n, i32* nocapture %A) local_unnamed_addr #0 {
+entry:
+  %cmp5 = icmp sgt i32 %n, 0
+  br i1 %cmp5, label %for.body.preheader, label %for.cond.cleanup
+
+for.body.preheader:                               ; preds = %entry
+  %wide.trip.count = zext i32 %n to i64
----------------
This IR is very messy, Clang-output IR does not always make for clean test cases. We don't need Function Attrs comments, we don't need press comments, many of the attributes are unnecessary, and the ones that are are best done inline. IR tests should be minimal, ideally from-scratch, but whittling Clang-produced IR down to something that could feasibly have been hand-written (or generated by a simple tool, like RVV and RVA tests) is fine.


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Comment at: llvm/test/Transforms/LoopVectorize/RISCV/riscv-interleaved.ll:4
+; CHECK-LABEL: foo
+; CHECK: LV: IC is 2
+
----------------
luke957 wrote:
> craig.topper wrote:
> > Why are we not checking the generated IR?
> Checking the generated IR is better.
Why is this not using update_test_checks.py?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D101469/new/

https://reviews.llvm.org/D101469