[PATCH] D103912: LoadStoreVectorizer: support different operand orders in the add sequence match

[Viacheslav Nikolaev via Phabricator via llvm-commits]

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First we refactor the code which does no wrapping add sequences
match: we need to allow different operand orders for
the key add instructions involved in the match.

Then we use the refactored code trying 4 variants of matching operands.

Originally the code relied on the fact that the matching operands
of the two last add instructions of memory index calculations 
had the same LHS argument. But which operand is the same
in the two instructions is actually not essential, so now we allow
that to be any of LHS or RHS of each of the two instructions.
This increases the chances of vectorization to happen.


https://reviews.llvm.org/D103912

Files:
  llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
  llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add.ll

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