[PATCH] D101469: [RISCV] Enable interleaved vectorization for RVV

Mon Jun 7 19:33:53 PDT 2021

luke957 added a comment.

In D101469#2801793 <https://reviews.llvm.org/D101469#2801793>, @luke957 wrote:

> In D101469#2801767 <https://reviews.llvm.org/D101469#2801767>, @craig.topper wrote:
>
>> I just noticed that this enabled interleaving in the loop vectorizer even when the V extension isn't enabled. So we now generate interleaved scalar code in some cases. Was that intentional?
>
> Thanks for reminding me. Sorry for my carelessness.

Fixed in https://reviews.llvm.org/D103787

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101469/new/

https://reviews.llvm.org/D101469