[llvm] 0aa9416 - [RISCV] Use bitfields to shrink the size of the vector load/store intrinsics to pseudo instruction lookup tables.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-06-07T17:57:51-07:00
New Revision: 0aa941654fc06d76d4fea57ea1b205f93dce391b

URL: https://github.com/llvm/llvm-project/commit/0aa941654fc06d76d4fea57ea1b205f93dce391b
DIFF: https://github.com/llvm/llvm-project/commit/0aa941654fc06d76d4fea57ea1b205f93dce391b.diff

LOG: [RISCV] Use bitfields to shrink the size of the vector load/store intrinsics to pseudo instruction lookup tables.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index 70480d14eba5..e8b79b008fa4 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -94,67 +94,67 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
 
 namespace RISCV {
 struct VLSEGPseudo {
-  uint8_t NF;
-  uint8_t Masked;
-  uint8_t Strided;
-  uint8_t FF;
-  uint8_t Log2SEW;
-  uint8_t LMUL;
+  uint16_t NF : 4;
+  uint16_t Masked : 1;
+  uint16_t Strided : 1;
+  uint16_t FF : 1;
+  uint16_t Log2SEW : 3;
+  uint16_t LMUL : 3;
   uint16_t Pseudo;
 };
 
 struct VLXSEGPseudo {
-  uint8_t NF;
-  uint8_t Masked;
-  uint8_t Ordered;
-  uint8_t Log2SEW;
-  uint8_t LMUL;
-  uint8_t IndexLMUL;
+  uint16_t NF : 4;
+  uint16_t Masked : 1;
+  uint16_t Ordered : 1;
+  uint16_t Log2SEW : 3;
+  uint16_t LMUL : 3;
+  uint16_t IndexLMUL : 3;
   uint16_t Pseudo;
 };
 
 struct VSSEGPseudo {
-  uint8_t NF;
-  uint8_t Masked;
-  uint8_t Strided;
-  uint8_t Log2SEW;
-  uint8_t LMUL;
+  uint16_t NF : 4;
+  uint16_t Masked : 1;
+  uint16_t Strided : 1;
+  uint16_t Log2SEW : 3;
+  uint16_t LMUL : 3;
   uint16_t Pseudo;
 };
 
 struct VSXSEGPseudo {
-  uint8_t NF;
-  uint8_t Masked;
-  uint8_t Ordered;
-  uint8_t Log2SEW;
-  uint8_t LMUL;
-  uint8_t IndexLMUL;
+  uint16_t NF : 4;
+  uint16_t Masked : 1;
+  uint16_t Ordered : 1;
+  uint16_t Log2SEW : 3;
+  uint16_t LMUL : 3;
+  uint16_t IndexLMUL : 3;
   uint16_t Pseudo;
 };
 
 struct VLEPseudo {
-  uint8_t Masked;
-  uint8_t Strided;
-  uint8_t FF;
-  uint8_t Log2SEW;
-  uint8_t LMUL;
+  uint16_t Masked : 1;
+  uint16_t Strided : 1;
+  uint16_t FF : 1;
+  uint16_t Log2SEW : 3;
+  uint16_t LMUL : 3;
   uint16_t Pseudo;
 };
 
 struct VSEPseudo {
-  uint8_t Masked;
-  uint8_t Strided;
-  uint8_t Log2SEW;
-  uint8_t LMUL;
+  uint16_t Masked :1;
+  uint16_t Strided : 1;
+  uint16_t Log2SEW : 3;
+  uint16_t LMUL : 3;
   uint16_t Pseudo;
 };
 
 struct VLX_VSXPseudo {
-  uint8_t Masked;
-  uint8_t Ordered;
-  uint8_t Log2SEW;
-  uint8_t LMUL;
-  uint8_t IndexLMUL;
+  uint16_t Masked : 1;
+  uint16_t Ordered : 1;
+  uint16_t Log2SEW : 3;
+  uint16_t LMUL : 3;
+  uint16_t IndexLMUL : 3;
   uint16_t Pseudo;
 };