[llvm] 8c6bd6c - [RISCV] Don't enable loop vectorizer interleaving if the V extension isn't enabled.

Craig Topper via llvm-commits llvm-commits at lists.llvm.org
Mon Jun 7 10:21:20 PDT 2021


Author: Craig Topper
Date: 2021-06-07T10:20:59-07:00
New Revision: 8c6bd6c22f384cc09e4a97de630ae63d7721dfd0

URL: https://github.com/llvm/llvm-project/commit/8c6bd6c22f384cc09e4a97de630ae63d7721dfd0
DIFF: https://github.com/llvm/llvm-project/commit/8c6bd6c22f384cc09e4a97de630ae63d7721dfd0.diff

LOG: [RISCV] Don't enable loop vectorizer interleaving if the V extension isn't enabled.

This can cause the vectorizer to generate interleaved scalar
code which might be ok for some CPUs, but definitely not all.
Disable it to restore the previous scalar behavior.

Differential Revision: https://reviews.llvm.org/D103787

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSubtarget.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 33d708fbf609b..ce36331e044d1 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -135,7 +135,9 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
     assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
     return UserReservedRegister[i];
   }
-  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
+  unsigned getMaxInterleaveFactor() const {
+    return hasStdExtV() ? MaxInterleaveFactor : 1;
+  }
 
 protected:
   // GlobalISel related APIs.


        


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