[PATCH] D102467: [RISCV] Implement codegen patterns for RVP ALU operations

Jim Lin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jun 7 03:07:33 PDT 2021


Jim updated this revision to Diff 350222.
Jim added a comment.

Add codegen patterns for logic operation with immediate.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D102467/new/

https://reviews.llvm.org/D102467

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoP.td
  llvm/test/CodeGen/RISCV/rvp/vector-alu.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D102467.350222.patch
Type: text/x-patch
Size: 76317 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210607/2416d352/attachment-0001.bin>


More information about the llvm-commits mailing list