[PATCH] D103213: [AMDGPU] All GWS instructions need aligned VGPR on gfx90a

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:4678-4692
+    const MachineOperand &CurOp = MI.getOperand(OpIdx);
+    const auto *RC = RI.getRegClassForReg(MRI, MO->getReg());
+    if (ST.needsAlignedVGPRs() && CurOp.isReg() && &CurOp != MO) {
+      const auto *CurRC = RI.getRegClassForReg(MRI, CurOp.getReg());
+      if (RI.isAlignedRC(CurRC) && RI.hasVectorRegisters(RC)) {
+        unsigned Sub = MO->getSubReg();
+        if (Sub &&
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arsenm wrote:
> Why can't you use the same hack as is used for AGPR returns?
How does it help here? The RC is selected correctly, but then operand folding substritutes odd subreg. For that reason I have to handlle it in the isOperandLegal() (here). Remove this code and test gws_init_odd_agpr will fail.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103213/new/

https://reviews.llvm.org/D103213