[PATCH] D96661: [RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 6 12:07:25 PDT 2021
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2721
+ unsigned Width = Op.getValueType() == MVT::i64 ? 64 : 32;
+ if (ShAmt >= Width && !isPowerOf2_64(ShAmt))
return None;
----------------
RKSimon wrote:
> @craig.topper Shouldn't this always early-out if ShAmt >= Width? Reported by coverity.
You mean should that be an || instead of &&?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D96661/new/
https://reviews.llvm.org/D96661
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