[PATCH] D96661: [RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2721
+  unsigned Width = Op.getValueType() == MVT::i64 ? 64 : 32;
+  if (ShAmt >= Width && !isPowerOf2_64(ShAmt))
     return None;
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@craig.topper Shouldn't this always early-out if ShAmt >= Width? Reported by coverity.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D96661/new/

https://reviews.llvm.org/D96661