[PATCH] D103427: [X86] Fix handling of maskmovdqu in X32
Harald van Dijk via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 5 15:38:58 PDT 2021
hvdijk updated this revision to Diff 350081.
hvdijk added a comment.
After adding a new test for the disassembly of these instructions, I found that I had not fully tested my previous version's attempt at disassembling: it only correctly handled the disassembly of addr32 maskmovdqu, not that of addr32 vmaskmovdqu. This version fixes it and adds tests for it. The instruction classes confuse me, so I may have missed a simpler way of achieving the same result.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D103427/new/
https://reviews.llvm.org/D103427
Files:
llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
llvm/lib/Target/X86/X86InstrSSE.td
llvm/lib/Target/X86/X86ScheduleBtVer2.td
llvm/test/CodeGen/X86/maskmovdqu.ll
llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
llvm/test/MC/X86/maskmovdqu.s
llvm/test/MC/X86/maskmovdqu64.s
llvm/utils/TableGen/X86DisassemblerTables.cpp
llvm/utils/TableGen/X86RecognizableInstr.cpp
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