[PATCH] D103211: [RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 348577.
craig.topper added a comment.

Rebase after pre-commiting tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103211/new/

https://reviews.llvm.org/D103211

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll

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